U-Boot mainline: Digilent Zybo-Z7 support

[Johannes Krottmayer]

On 01.06.20 at 10:18,  Michal Simek wrote:
> SPL is community effort and not supported flow by Xilinx. If you want to
> use it, use it but don't expect any help from Xilinx to help you with
> issues. I take care about it, use it but there is no planning behind. I
> am fixing issues for me and for the rest please send a patch and I will
> take a look. As far as I know JTAG, SD and qspi(but limited) flows
> should work. I use SD boot most of the time.

Thanks for the clarification.

> If you want to pack bitstream to u-boot.img/itb then it should be quite
> easy to do and all things are in place.

How is the official U-Boot way, to use the created image on ZYNQ boards
or which generated files must be placed on a SD card? Unfortunately I
couldn't find any information in the docs at this time. I have tried to
create the image with the (custom) bitstream file. Used a FIT source
(based on <arch/arm/mach-zynqmp/mkimage_fit_atf.sh>) which I have
attached. But I have no idea how place the image on the SD card. Tried a
simple...

$ dd=if=/path/to/U-Boot/u-boot.img of=/dev/sdf

but didn't work. Also tried to rename the image to BOOT.BIN and place it
in the root directory of a FAT32 filesystem.

When I use the Xilinx tools to generate the image with following, it
works:

* Vivado: Create bitstream from design
* Vitis: Create and build FSBL
* Build U-Boot
* Create BIF:

image {
[bootloader]fsbl.elf
fpga.bit
u-boot.elf
}

* Use bootgen to create the image
* Create FAT32 filesystem on SD card
* Place generated image (BOOT.BIN) to root directory

Kind regards,
Johannes K.
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// SPDX-License-Identifier: (BSD-2-Clause)

/dts-v1/;

/ {
	description = "Configuration to load custom Xilinx FPGA bitstreams";

	images {
		uboot {
			description = "U-Boot (32-bit)";
			data = /incbin/("u-boot-nodtb.bin");
			type = "firmware";
			os = "u-boot";
			arch = "arm";
			compression = "none";
			load = <0x4000000>;
			entry = <0x4000000>;
			hash {
				algo = "md5";
			};
		};
		fpga {
			description = "Xilinx FPGA Bitstream";
			data = /incbin/("/home/krj/projects/xilinx/ZYBO_Z7/fpga.bit");
			type = "fpga";
			arch = "arm";
			compression = "none";
			hash {
				algo = "md5";
			};
		};
		fdt_1 {
			description = "zynq-zc702";
			data = /incbin/("arch/arm/dts/zynq-zybo-z7.dtb");
			type = "flat_dt";
			arch = "arm";
			compression = "none";
			load = <0x100000>;
			hash {
				algo = "md5";
			};
		};
	};
	configurations {
		default = "config_1";

	};
};