[PATCH] rockchip: Add delay after link-training

[Kurt Miller]

On at least the RockPro64, many cards will trip a
synchronous abort when first accessing PCIe config space
during bus scanning. A delay after link training allows
some of these cards to function.

Signed-off-by: Kurt Miller <kurt at intricatesoftware.com>
---
On the RockPro64, some pci cards trip a synchronous abort when scanning the
pci bus. For example with HighPoint Rocket Raid 640L which is based on
Marvell 88SE9230 I see this:

=> pci
"Synchronous Abort" handler, esr 0x96000210
elr: 000000000022d034 lr : 000000000022cfd0 (reloc)
elr: 00000000f4568034 lr : 00000000f4567fd0
x0 : 0000000000100000 x1 : 00000000f8000000
x2 : 0000000000000000 x3 : 0000000000100000
x4 : 00000000f2559290 x5 : 0000000000000000
x6 : 0000000000000001 x7 : 00000000f2559860
x8 : 0000000000000030 x9 : 0000000000000008
x10: 0000000000000010 x11: 00000000f251fd1c
x12: 0000000000001421 x13: 0000000000001468
x14: 00000000f251fd4c x15: 00000000ffffffff
x16: 0000000000060001 x17: 000000000000001f
x18: 00000000f2532dc0 x19: 00000000f251fcd0
x20: 0000000000000001 x21: 0000000000000000
x22: 0000000000010000 x23: 00000000f45d4000
x24: 0000000000000000 x25: 00000000f45bc000
x26: 0000000000000000 x27: 0000000000000000
x28: 00000000f2541440 x29: 00000000f251fc20

Code: 540000c1 350000a5 93407c00 f9400081 (b8616800)
Resetting CPU ...

Adding a delay after link training works-around the problem. I added this
delay to the OpenBSD rkpcie driver as well:

https://github.com/openbsd/src/commit/9857dee3520d8ca5bec68538f4b0708d7e64fc87

HighPoint Rocket Raid 640L needs a 1.75 sec delay and Crossfield SAS9211-4i
needs a 1 second delay, so I arbitrarily decided on 2 seconds.

The delay work-around was originally discovered by nuumio:
https://github.com/nuumio/linux-kernel/commit/5a65b17686002dc84d461bffa324a2cb68e67aee

 drivers/pci/pcie_rockchip.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 0edc2464a8..51cfbf6b18 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -288,6 +288,14 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 		goto err_power_off_phy;
 	}
 
+	/*
+	 * XXX: On at least the RockPro64, many cards will trip a
+	 * synchronous abort when first accessing PCIe config space
+	 * during bus scanning. A delay after link training allows
+	 * some of these cards to function.
+	 */
+	mdelay(2000);
+
 	/* Initialize Root Complex registers. */
 	writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
 	writel(PCI_CLASS_BRIDGE_PCI << 16,
-- 
2.26.2