[PATCH v13 00/19] RISC-V SiFive FU540 support SPL

Tue Jun 2 20:56:41 CEST 2020

Hi Rick,

On Fri, May 29, 2020 at 11:34 AM Pragnesh Patel
<pragnesh.patel at sifive.com> wrote:
>
> This series add support for SPL to FU540. U-Boot SPL can boot from
> L2 LIM (0x0800_0000) and jump to OpenSBI(FW_DYNAMIC firmware) and
> U-Boot proper from MMC devices.
>
> This series is also available here [1] for testing
> [1] https://github.com/pragnesh26992/u-boot/tree/spl
>
> How to test this patch:
> 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y
> 2) export OPENSBI=<path to opensbi/build/platform/generic/firmware/fw_dynamic.bin>
> 3) Change to u-boot-dir
> 4) make sifive_fu540_defconfig
> 5) make all
> 6) Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
>
>         # sudo sgdisk --clear \
>         > --set-alignment=2 \
>         > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
>         > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
>         > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
>         > /dev/sda
>
> 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
> 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082
>
> Changes in v13:
> - Add a new patch to set the ethernet clock rate
>   (riscv: sifive: dts: fu540: set ethernet clock rate)
>
> Changes in v12:
> - Rebase on mainline U-Boot
>   Added necessary include files which are not part of common header now
>   Remove unnecessary include files
>
>   drivers/misc/sifive-otp.c
>         +#include <linux/bitops.h>
>         +#include <linux/delay.h>
>
>   board/sifive/fu540/fu540.c
>         -#include <common.h>
>         +#include <log.h>
>
>   board/sifive/fu540/spl.c
>         +#include <init.h>
>         +#include <log.h>
>         +#include <linux/delay.h>
>
>   drivers/ram/sifive/fu540_ddr.c
>         +#include <linux/bitops.h>
>
>   arch/riscv/cpu/fu540/cpu.c
>         -#include <common.h>
>         +#include <asm/cache.h>
>
>   arch/riscv/cpu/fu540/spl.c
>         -#include <common.h>
>         +#include <log.h>
>
>   board/sifive/fu540/spl.c
>         -#include <common.h>
>         +#include <init.h>
>         +#include <log.h>
>         +#include <linux/delay.h>
>
> - Update commit description for Release ethernet clock reset
> - Update OpenSBI building section in "doc/board/sifive/fu540.rst"
>
> Changes in v11:
> - Remove TPL related code and OF_PLATDATA from FU540
>   DDR driver (drivers/ram/sifive/fu540_ddr.c)
> - Update FU540 doc (doc/board/sifive/fu540.rst)
>   Remove unnecessary print
>
> Changes in v10:
> - Update commit description for ethernet clock reset
>   (https://patchwork.ozlabs.org/patch/1289003)
> - Update commit description for ddr clock initialization
>   (https://patchwork.ozlabs.org/patch/1289000)
>
> Changes in v9:
> - Remove cache related patches from this series
>   sifive: dts: fu540: Enable L2 Cache in U-Boot
>   (https://patchwork.ozlabs.org/patch/1286705)
>   riscv: sifive: fu540: enable all cache ways from U-Boot proper
>   (https://patchwork.ozlabs.org/patch/1286706)
> - Rename SiFive DDR driver from sdram_fu540.c to fu540_ddr.c
>   and also do some typo correction in driver
> - Remove CONFIG_SPL_BUILD for __prci_ddr_release_reset()
> - Release ethernet clock reset instead of ethernet clock
>   initialization
>   (https://patchwork.ozlabs.org/patch/1286697)
> - Squash fu540 cpu patches
>   (https://patchwork.ozlabs.org/patch/1286699)
>   (https://patchwork.ozlabs.org/patch/1286700)
> - Use spl_boot_device() instead of board_boot_order()
>
> Changes in v8:
> - Remove SPL_CRC7_SUPPORT Kconfig option and compile
>   crc7.o when CONFIG_MMC_SPI selected
> - Add "TODO" in drivers/ram/sifive/sdram_fu540.c
> - Remove unnecessary TODO from drivers/clk/sifive/fu540-prci.c
> - Make fu540-hifive-unleashed-a00-sdram-ddr4.dtsi file dual-licensed
> - Add 2 new patches
>   sifive: fu540: Add sample SD gpt partition layout
>   (https://patchwork.ozlabs.org/patch/1092)
>   sifive: fu540: Add U-Boot proper sector start
>   (https://patchwork.ozlabs.org/patch/1093)
> - Remove patch
>   riscv: Enable cpu clock if it is present
>   (https://patchwork.ozlabs.org/patch/1281573)
> - Update doc/board/sifive/fu540.rst for PLATFORM=generic
>
> Changes in v7:
> - Standardize SD gpt partition layout
> - Add delay for SiFive OTP driver
> - Use DM way for corepll and ddrpll
> - Add new cpu fu540 (arch/riscv/cpu/fu540)
> - Update document for FU540 (doc/board/sifive/fu540.rst)
>
> Changes in v6:
> - Typo Correction
> - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi
>   Dual Licensed
> - Sync Hifive unleashed dts from Linux
> - Add arch/riscv/fu540 for FU540 specific code
>
> Changes in v5:
> - Return read/write bytes for sifive_otp_read and sifive_otp_write
> - Correct Palmer's email address
>
> Changes in v4:
> - Split misc DM driver patch into multiple patches
> - Added new SPL_CRC7_SUPPORT Kconfig option
> - Added DM driver for DDR
> - Added clk_enable and clk_disable ops in SiFive PRCI driver
> - Added early clock initialization for SPL in SiFive PRCI driver
> - Added early clock initialization for SPL in SiFive PRCI driver
> - Added SPL config options in sifive_fu540_defconfig instead of
>   creatiing a new config file for SPL
> - Update fu540.rst on how to build and flash U-boot SPL
>
> Changes in v3:
> - Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/
> - Split SPL patches into DDR and SPL and spl defconfig
> - Update fu540/MAINTAINERS file
> - Update fu540.rst on how to build and flash U-boot SPL
>
> Changes in v2:
> - Add DM driver Sifive OTP
> - Split SPL patches into multiple patches
> - Add a seprate patch for _image_binary_end and crc7.c
> - Add a seprate patch to add board -u-boot.dtsi files
> - Update FU540 RISC-V documentation
>
>
> Jagan Teki (2):
>   sifive: fu540: Add sample SD gpt partition layout
>   sifive: fu540: Add U-Boot proper sector start
>
> Pragnesh Patel (17):
>   misc: add driver for the SiFive otp controller
>   riscv: sifive: fu540: Use OTP DM driver for serial environment
>     variable
>   riscv: Add _image_binary_end for SPL
>   lib: Makefile: build crc7.c when CONFIG_MMC_SPI
>   riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
>   sifive: fu540: add ddr driver
>   sifive: dts: fu540: Add DDR controller and phy register settings
>   riscv: sifive: dts: fu540: add U-Boot dmc node
>   clk: sifive: fu540-prci: Add clock enable and disable ops
>   clk: sifive: fu540-prci: Add ddr clock initialization
>   clk: sifive: fu540-prci: Release ethernet clock reset
>   riscv: sifive: dts: fu540: set ethernet clock rate
>   riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux
>   riscv: cpu: fu540: Add support for cpu fu540
>   riscv: sifive: fu540: add SPL configuration
>   configs: fu540: Add config options for U-Boot SPL
>   doc: sifive: fu540: Add description for OpenSBI generic platform

Any plan to pull this for the release?

Jagan.