[PATCH v3 1/2] mtd: rawnand: ca_nand: add Cortina Access Parallel NAND controller support

[Alex Nemirovsky]

> On Jun 2, 2020, at 12:20 AM, Miquel Raynal <miquel.raynal at bootlin.com> wrote:
> 
> Hi Alex,
> 
> Alex Nemirovsky <alex.nemirovsky at cortina-access.com> wrote on Mon,  1
> Jun 2020 14:26:49 -0700:
> 
>> From: Jason Li <jason.li at cortina-access.com>
>> 
>> Supports all CAxxxx SoCs which support a parallel nand controller.
>> It should be noted that some CAxxxx Soc also support an separate
>> SPI serial NAND controller.
>> 
>> This driver only supports the parallel NAND controller. A different
>> driver supports the SPI NAND interface controller.
>> 
>> Signed-off-by: Jason Li <jason.li at cortina-access.com>
>> Signed-off-by: Alex Nemirovsky <alex.nemirovsky at cortina-access.com>
>> 
>> CC: Miquel Raynal <miquel.raynal at bootlin.com>
>> CC: Simon Glass <sjg at chromium.org>
>> CC: Tom Rini <trini at konsulko.com>
>> ---
>> 
>> Changes in v3:
>> - Include udelay.h to avoid implicit declaration of udelay()
>> 
>> Changes in v2:
>> - Cleanup code style to pass checkpatch.pl
>> 
>> MAINTAINERS                    |    2 +
>> drivers/mtd/nand/raw/Kconfig   |   31 +
>> drivers/mtd/nand/raw/Makefile  |    1 +
>> drivers/mtd/nand/raw/ca_nand.c | 4943 ++++++++++++++++++++++++++++++++++++++++
>> drivers/mtd/nand/raw/ca_nand.h | 3899 +++++++++++++++++++++++++++++++
> 
> This is insanely big !

Hi Miquel, could you clarify?  Is there a change request?
> 
>> 5 files changed, 8876 insertions(+)
>> create mode 100644 drivers/mtd/nand/raw/ca_nand.c
>> create mode 100644 drivers/mtd/nand/raw/ca_nand.h
>> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 8add9d4..6da2ad8 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -181,6 +181,8 @@ F:	drivers/gpio/cortina_gpio.c
>> F:	drivers/watchdog/cortina_wdt.c
>> F:	drivers/serial/serial_cortina.c
>> F:	drivers/mmc/ca_dw_mmc.c
>> +F:	drivers/mtd/nand/raw/ca_nand.c
>> +F:	drivers/mtd/nand/raw/ca_nand.h
>> 
>> ARM/CZ.NIC TURRIS MOX SUPPORT
>> M:	Marek Behun <marek.behun at nic.cz>
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index c4d9d31..b3cbfcc 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -102,6 +102,37 @@ config NAND_BRCMNAND_63158
>>        help
>>          Enable support for broadcom nand driver on bcm63158.
>> 
>> +config NAND_CORTINA
>> +        tristate "Support Cortina-Access Parallel NAND cntlr."
>> +	select SYS_NAND_SELF_INIT
> 
> Alignment looks wrong
> 
>> +        help
>> +          This enables the parallel RAW NAND driver for the
>> +	  Cortina-Access CAxxxx Family of SoCs.
>> +
>> +config NAND_CORTINA_ECC_LEVEL
>> +        int "Cortina-Access Parallel Nand driver HW ECC algorithm"
>> +        default 3
>> +        range 0 5
>> +        depends on NAND_CORTINA
>> +        help
>> +          NAND Flash ECC algorithm. Value range from 0 to 5.
>> +          The default value is 3.
>> +
>> +          0: Hamming algorithm. Correct 3 bad bits in 256 btyes.
>> +          1: Hamming algorithm. Correct 3 bad bits in 512 btyes.
>> +          2: BCH algorithm. Correct 8 bad bits in 1K btyes.
>> +          3: BCH algorithm. Correct 16 bad bits in 1K btyes.
>> +          4: BCH algorithm. Correct 24 bad bits in 1K btyes.
>> +          5: BCH algorithm. Correct 40 bad bits in 1K btyes.
> 
> Not sure how u-boot guys want to handle this but the current way to
> request for a specif correction is to pass nand-ecc-strength and
> nand-ecc-size DT properties. If the driver does not support the
> requested properties, there is a function (at least in Linux) which
> finds the closest correction called nand_ecc_choose_conf(), provided
> that you implemented a few specific hooks in your driver.
> 
> But basically, this should be the core's input, not the user, unless
> you have a strong reason to do so.
> 
>> +
>> +config NAND_CORTINA_ECC_HW_BCH
>> +     bool
>> +     default y
>> +     depends on NAND_CORTINA_ECC_LEVEL=2 \
>> +             || NAND_CORTINA_ECC_LEVEL=3 \
>> +             || NAND_CORTINA_ECC_LEVEL=4 \
>> +             || NAND_CORTINA_ECC_LEVEL=5
>> +
>> config NAND_DAVINCI
>> 	bool "Support TI Davinci NAND controller"
>>