[PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns

[Tan, Ley Foon]

> -----Original Message-----
> From: Marek Vasut <marex at denx.de>
> Sent: Friday, June 5, 2020 8:52 PM
> To: Tan, Ley Foon <ley.foon.tan at intel.com>; u-boot at lists.denx.de
> Cc: Ley Foon Tan <lftan.linux at gmail.com>; See, Chin Liang
> <chin.liang.see at intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Ang, Chee Hong
> <chee.hong.ang at intel.com>
> Subject: Re: [PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-
> time-ns
> 
> On 6/5/20 10:21 AM, Ley Foon Tan wrote:
> > Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing
> > calculation") change the hcnt and lcnt timing calculation.
> >
> > After this new timing calculation, hcnt will have negative value with
> > i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.
> Shouldn't either the driver or the calculation be fixed instead ?
The original timing calculation in driver doesn't take fall time or rise time into calculation.
The new i2c timing calculation is based on calculation from Designware i2c databook. So, I don't think need fix in driver.

Regards
Ley Foon