U-Boot atheros PHY support and cubox ethernet
Fabio Estevam
festevam at gmail.com
Wed Jun 17 23:28:37 CEST 2020
Hi Tom,
On Wed, Jun 17, 2020 at 4:00 PM Tom Rini <trini at konsulko.com> wrote:
> Based on your follow-up patches, I think you'll be unsurprised it
> doesn't work. I get:
> Net: Could not get PHY for FEC0: addr 0
Now I understand why the PHY could not be found with the patches I sent.
On mx6cubox the AR8035 is clocked from a 25MHz clock coming from the
i.MX6 GPIO16 pin.
My patch incorrectly removed this setting.
> + int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
> + if (ret)
> + return ret;
> +
> + /* set gpr1[ENET_CLK_SEL] */
> + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
enable_fec_anatop_clock() and GPR1 settings above must remain.
In order to get patch 1 to work (the one that adds the
qca,clk-out-frequency property ) you also need this FEC change:
https://pastebin.com/raw/mcKdwwTs
I hope this helps.
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