[PATCH v3 0/4] update clock handler and proper cpu features
Sagar Kadam
sagar.kadam at sifive.com
Fri Jun 19 11:07:28 CEST 2020
Hello Rick,
> -----Original Message-----
> From: Rick Chen <rickchen36 at gmail.com>
> Sent: Friday, June 19, 2020 1:26 PM
> To: Sagar Kadam <sagar.kadam at sifive.com>
> Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Lukasz Majewski
> <lukma at denx.de>; Bin Meng <bmeng.cn at gmail.com>; Jagan Teki
> <jagan at amarulasolutions.com>; Pragnesh Patel
> <pragnesh.patel at sifive.com>; Anup Patel <anup.patel at wdc.com>; Simon
> Glass <sjg at chromium.org>; Sean Anderson <seanga2 at gmail.com>; rick
> <rick at andestech.com>; ycliang at andestech.com; Alan Kao
> <alankao at andestech.com>
> Subject: Re: [PATCH v3 0/4] update clock handler and proper cpu features
>
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>
> Hi Sagar
>
> > From: Sagar Shrikant Kadam [mailto:sagar.kadam at sifive.com]
> > Sent: Thursday, June 04, 2020 6:45 PM
> > To: u-boot at lists.denx.de; Rick Jian-Zhi Chen(陳建志); lukma at denx.de
> > Cc: bmeng.cn at gmail.com; jagan at amarulasolutions.com;
> pragnesh.patel at sifive.com; anup.patel at wdc.com; sjg at chromium.org;
> seanga2 at gmail.com; Sagar Shrikant Kadam
> > Subject: [PATCH v3 0/4] update clock handler and proper cpu features
> >
> > U-Boot cmd "cpu detail" shows inconsistent CPU features and is missing
> clk_request and free handlers.
> > The current "cpu detail" sometimes shows "Microcode" as a feature,
> which is not the case with FU540-C000 on HiFive Unleashed board.
> >
> > Patch 1: add clk request handler to check if valid clock id is requested.
> > Patch 2: add cpu node aliases.
> > Patch 3: Correctly parse and update mmu-type.
> >
> > RISC-V core's on FU540-C000 SoC have separate instruction and data
> (split)
> > L1 cache.
> > Patch 4:Use i-cache-size dt property as one of identifier to indicate a
> > split cache is available.
> >
> > I have picked few dependent patches from Sean's and Pragnesh's latest
> series from here [1]...[5].
> >
> > These have applied on mainline U-Boot commit 0d8f35b58cc8 ("Merge
> https://gitlab.denx.de/u-boot/custodians/u-boot-spi")
> >
> > Patch history:
> > =============================================
> > V3:
> > 1. Included the cosmetic change as suggested
> > s/L1 feature/L1 cache feature/
> > 2. Added Reviewed-By tags
> >
> > V2:
> > 1. Incorporate review comments from Bin and Sean Anderson.
> > and dropped 2nd patch as similar work was already done in [1] and [2]
> > 2 Add cpu node aliases to display cpu node's in sequence.
> > 3. Add fix to show mmu as available cpu feature.
> > 4. Check and append L1 cache feature.
> >
> > V1: Base version
> > Thanks to Vincent Chen <vincent.chen at sifive.com> for testing the V1
> > version of this series.
> >
> > [1] https://patchwork.ozlabs.org/patch/1295345
> > [2] https://patchwork.ozlabs.org/patch/1295346
> > [3] https://patchwork.ozlabs.org/patch/1300369
> > [4] https://patchwork.ozlabs.org/patch/1300370
> > [5] https://patchwork.ozlabs.org/patch/1300373
> >
> > All these together is available here:
> > https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v3
> >
> > Sagar Shrikant Kadam (4):
> > fu540: prci: add request and free clock handlers
> > riscv: dts: hifive-unleashed-a00: add cpu aliases
> > riscv: cpu: fixes to display proper CPU features
> > riscv: cpu: check and append L1 cache to cpu features
> >
> > arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++
> > drivers/clk/sifive/fu540-prci.c | 21 +++++++++++++++++++++
> > drivers/cpu/riscv_cpu.c | 10 +++++++++-
> > 3 files changed, 35 insertions(+), 1 deletion(-)
>
>
> I am trying to apply to u-boot/master, but it fail as below:
> Applying: fu540: prci: add request and free clock handlers
> error: patch failed: drivers/clk/sifive/fu540-prci.c:581
> error: drivers/clk/sifive/fu540-prci.c: patch does not apply
> Patch failed at 0001 fu540: prci: add request and free clock handlers
>
> Please rebase master, I will sync to master later.
>
Sure, I will rebase and resend this series on master
Thanks & BR,
Sagar
> Thanks,
> Rick
>
> >
> > --
> > 2.7.4
> >
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