[PATCH v4 0/4] update clock handler and proper cpu features

[Bin Meng]

Hi Sagar,

On Sun, Jun 21, 2020 at 9:10 PM Sagar Shrikant Kadam
<sagar.kadam at sifive.com> wrote:
>
> U-Boot cmd "cpu detail" shows inconsistent CPU features and is missing
> clk_request and free handlers.
> The current "cpu detail" sometimes shows "Microcode" as a feature, which
> is not the case with FU540-C000 on HiFive Unleashed board.
>
> Patch 1: add clk request handler to check if valid clock id is requested.
> Patch 2: add cpu node aliases.
> Patch 3: Correctly parse and update mmu-type.
>
> RISC-V core's on FU540-C000 SoC have separate instruction and data (split)
> L1 cache.
> Patch 4:Use i-cache-size dt property as one of identifier to indicate a
>         split cache is available.
>
> I have picked few dependent patches from Sean's series from here [1]
> and [2].
>
> These have applied on mainline U-Boot commit 2b8692bac1e8 ("Merge tag
> 'efi-2020-07-rc5-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi")
>
> Patch history:
> =============================================
> V4:
> 1. Rebased the series to mainline commit.
> 2. Updated dependency list as few patches are now merged.
> 3. Added U-Boot log of the flow i.e fsbl + fw_payload.bin (Opensbi+U-Boot)
>
> V3:
> 1. Included the cosmetic change as suggested
>    s/L1 feature/L1 cache feature/
> 2. Added Reviewed-By tags
>
> V2:
> 1. Incorporate review comments from Bin and Sean Anderson.
>    and dropped 2nd patch as similar work was already done in [1] and [2]
> 2  Add cpu node aliases to display cpu node's in sequence.
> 3. Add fix to show mmu as available cpu feature.
> 4. Check and append L1 cache feature.
>
> V1: Base version
>     Thanks to Vincent Chen <vincent.chen at sifive.com> for testing the V1
>     version of this series.
>
> [1] https://patchwork.ozlabs.org/patch/1295345
> [2] https://patchwork.ozlabs.org/patch/1295346
>
> All these together is available here:
> https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v4
>
> U-Boot log:
> ===========================================================
> SiFive FSBL:       2020-02-19-1081db9-dirty
> Using new FSBL DTB now
> HiFive-U-serial-#: 000002c8
> Loading boot payload....
>
> OpenSBI v0.7-31-gd626037
>    ____                    _____ ____ _____
>   / __ \                  / ____|  _ \_   _|
>  | |  | |_ __   ___ _ __ | (___ | |_) || |
>  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
>  | |__| | |_) |  __/ | | |____) | |_) || |_
>   \____/| .__/ \___|_| |_|_____/|____/_____|
>         | |
>         |_|
>
> Platform Name          : SiFive Freedom U540
> Platform HART Features : RV64ACDFIMSU
> Platform HART Count    : 4
> Current HART ID        : 1
> Firmware Base          : 0x80000000
> Firmware Size          : 100 KB
> Runtime SBI Version    : 0.2
>
> MIDELEG : 0x0000000000000222
> MEDELEG : 0x000000000000b109
> PMP0    : 0x0000000080000000-0x000000008001ffff (A)
> PMP1    : 0x0000000000000000-0x0000007fffffffff (A,R,W,X)
>
>
> U-Boot 2020.07-rc4-00084-gf824d2c (Jun 21 2020 - 04:58:40 -0700)
>
> CPU:   rv64imac
> Model: SiFive HiFive Unleashed A00
> DRAM:  8 GiB
> MMC:   spi at 10050000:mmc at 0: 0
> In:    serial at 10010000
> Out:   serial at 10010000
> Err:   serial at 10010000
> Net:   eth0: ethernet at 10090000
> Hit any key to stop autoboot:  0
> => cpu detail
>   0: cpu at 0      rv64imac
>         ID = 0, freq = 999.100 MHz: L1 cache
>   1: cpu at 1      rv64imafdc
>         ID = 1, freq = 999.100 MHz: L1 cache, MMU
>   2: cpu at 2      rv64imafdc
>         ID = 2, freq = 999.100 MHz: L1 cache, MMU
>   3: cpu at 3      rv64imafdc
>         ID = 3, freq = 999.100 MHz: L1 cache, MMU
>   4: cpu at 4      rv64imafdc
>         ID = 4, freq = 999.100 MHz: L1 cache, MMU
> =>
>

It's strange that I am seeing different output without your patch:

=> cpu list
  1: cpu at 1      rv64imafdc
  2: cpu at 2      rv64imafdc
  0: cpu at 3      rv64imafdc
  3: cpu at 4      rv64imafdc
=> cpu detail
  1: cpu at 1      rv64imafdc
        ID = 1, freq = 12 Hz: L1 cache
  2: cpu at 2      rv64imafdc
        ID = 2, freq = 12 Hz: L1 cache
  0: cpu at 3      rv64imafdc
        ID = 3, freq = 12 Hz: L1 cache
  3: cpu at 4      rv64imafdc
        ID = 4, freq = 12 Hz: L1 cache

It looks like your patch included the E51 core (hartid 0) in the output?

Regards,
Bin