[PATCH 3/5] fu540: dtsi: add reset producer and consumer entries

[Sean Anderson]

On 6/22/20 8:27 AM, Sagar Shrikant Kadam wrote:
> The resets to DDR and ethernet sub-system are connected to
> PRCI device reset control register, these reset signals
> are active low and are held low at power-up. Add these reset
> producer and consumer details needed by the reset driver.
> 
> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
> Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>
> ---
>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> index 9bba554..b37241e 100644
> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> @@ -59,6 +59,16 @@
>  			reg = <0x0 0x2000000 0x0 0xc0000>;
>  			u-boot,dm-spl;
>  		};
> +		prci: clock-controller at 10000000 {

Shouldn't this have a compatible property?

> +			#reset-cells = <1>;
> +			resets = <&prci PRCI_RST_DDR_CTRL_N>,
> +				 <&prci PRCI_RST_DDR_AXI_N>,
> +				 <&prci PRCI_RST_DDR_AHB_N>,
> +				 <&prci PRCI_RST_DDR_PHY_N>,
> +				 <&prci PRCI_RST_GEMGXL_N>;
> +			reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
> +					"ddr_phy", "gemgxl_reset";
> +		};
>  		dmc: dmc at 100b0000 {
>  			compatible = "sifive,fu540-c000-ddr";
>  			reg = <0x0 0x100b0000 0x0 0x0800
> 

--Sean