[PATCH 4/5] sifive: reset: add DM based reset driver for SiFive SoC's

[Sean Anderson]

On 6/24/20 1:15 AM, Bin Meng wrote:
> Hi Sean,
> 
> On Wed, Jun 24, 2020 at 1:04 PM Sean Anderson <seanga2 at gmail.com> wrote:
>>
>> On 6/24/20 1:01 AM, Bin Meng wrote:
>>> Hi Sean,
>>>
>>> On Wed, Jun 24, 2020 at 12:17 PM Sean Anderson <seanga2 at gmail.com> wrote:
>>>>
>>>> On 6/22/20 8:27 AM, Sagar Shrikant Kadam wrote:
>>>>> The resets to DDR and ethernet sub-system are connected to
>>>>> PRCI device reset control register, these reset signals
>>>>> are active low and are held low at power-up. Add these reset
>>>>> producer and consumer details needed by the reset driver.
>>>>>
>>>>> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
>>>>> Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>
>>>>> ---
>>>>>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 10 ++++++++++
>>>>>  1 file changed, 10 insertions(+)
>>>>>
>>>>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>>>> index 9bba554..b37241e 100644
>>>>> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>>>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>>>> @@ -59,6 +59,16 @@
>>>>>                       reg = <0x0 0x2000000 0x0 0xc0000>;
>>>>>                       u-boot,dm-spl;
>>>>>               };
>>>>> +             prci: clock-controller at 10000000 {
>>>>
>>>> Shouldn't this have a compatible property?
>>>
>>> This is the U-Boot specific dts fragment. See fu540-c000.dtsi
>>
>> I ask because this node sits in /soc, and all the other nodes in /soc
>> have compatible strings. Since this device is bound by the clock driver,
>> perhaps it should be located under /soc/prci instead.
> 
> fu540-c000.dtsi has everything you asked.
> 

Ah, I didn't see that this was an extension. Looks good to me.

--Sean