[PATCH 4/5] sifive: reset: add DM based reset driver for SiFive SoC's

[Bin Meng]

On Mon, Jun 22, 2020 at 8:28 PM Sagar Shrikant Kadam
<sagar.kadam at sifive.com> wrote:
>
> PRCI module within SiFive SoC's has register with which we can
> reset the sub-systems within the SoC. The resets to DDR and ethernet
> sub systems within FU540-C000 SoC are active low, and are hold low
> by default on power-up. Currently these are directly asserted within
> prci driver via register read/write.
> With the DM based reset driver support here, we bind the reset
> driver with clock (prci) driver and assert the reset signals of
> both sub-system's appropriately.
>
> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
> Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>
> ---
>  arch/riscv/include/asm/arch-fu540/reset.h |  13 ++++
>  drivers/clk/sifive/fu540-prci.c           |  73 ++++++++++++++----
>  drivers/reset/reset-sifive.c              | 118 ++++++++++++++++++++++++++++++
>  3 files changed, 189 insertions(+), 15 deletions(-)
>  create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h
>  create mode 100644 drivers/reset/reset-sifive.c
>

Reviewed-by: Bin Meng <bin.meng at windriver.com>
Tested-by: Bin Meng <bin.meng at windriver.com>