U-Boot atheros PHY support and cubox ethernet

[Soeren Moch]

Hi Fabio,

On 25.06.20 01:19, Fabio Estevam wrote:
> Hi Soeren,
>
> On Wed, Jun 24, 2020 at 7:29 PM Soeren Moch <smoch at web.de> wrote:
>
>> Unfortunately I have no access to my usual development board (and will
>> not have until the v2020.07 release). I only can use an old board
>> without working USB-OTG, limited to eMMC boot. So I tried to avoid
>> bisecting, because a bad commit could completely brick this board.
> Ok, understood.
>
> We could check if the issue on your board is due to:
>
> commit 6333cbb3817ed551cd7d4e92f7359c73ccc567fc
> Author: Michael Walle <michael at walle.cc>
> Date:   Thu May 7 00:11:58 2020 +0200
>
>     phy: atheros: ar8035: remove static clock config
>
>     We can configure the clock output in the device tree. Disable the
>     hardcoded one in here. This is highly board-specific and should have
>     never been enabled in the PHY driver.
>
>     If bisecting shows that this commit breaks your board it probably
>     depends on the clock output of your Atheros AR8035 PHY. Please have a
>     look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
>     "clk-out-frequency = <125000000>" because that value was the hardcoded
>     value until this commit.
>
>     Signed-off-by: Michael Walle <michael at walle.cc>
>     Acked-by: Joe Hershberger <joe.hershberger at ni.com>
>
> On your board, are you able to measure with a scope the AR8035 CLK_25M pin?
>
> Prior to this commit the CLK_25M was hardcoded to output a 125MHz clock.
>
> Now that this setting from the ar8035 phy driver is gone we should
> pass this information in some form:
>
> - We tried via devicetree with the "qca,clk-out-frequency" property,
> but it did not work. This is an area where you could add some debug
> prints inside drivers/net/phy/atheros.c and see if if
> qca,clk-out-frequency is being parsed correctly to configure a 125MHz
> clock output. This is the method I used on mx6cuboxi last week and it
> works.
The phy-handle was missing in the fec node. With this added everything
works fine:

---8<---
diff --git a/arch/arm/dts/imx6q-tbs2910.dts b/arch/arm/dts/imx6q-tbs2910.dts
index cc5df37b46..5b9b025bb6 100644
--- a/arch/arm/dts/imx6q-tbs2910.dts
+++ b/arch/arm/dts/imx6q-tbs2910.dts
@@ -105,9 +105,20 @@
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
+       phy-handle = <&phy>;
        phy-mode = "rgmii-id";
        phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
        status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               phy: ethernet-phy at 4 {
+                       reg = <4>;
+                       qca,clk-out-frequency = <125000000>;
+               };
+       };
 };
 
 &hdmi {
---8<---
>
> - Other way to configure the AR803x is via board code. Please try to
> copy the ar8031_phy_fixup() and board_phy_config() from
> board/freescale/mx6sabresd/mx6sabresd.c into your board file.
>
> (I plan to remove this board PHY code in mx6sabresd after 2020.07 and
> use "qca,clk-out-frequency" to do the job).
OK, so I think we should use the dts patch as fix for u-boot now and
sync that to linux afterwards.
Do you want to send a proper patch for that? Otherwise I can do so.

Thanks for your help and suggestions,
Soeren