[PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on
Sagar Kadam
sagar.kadam at sifive.com
Thu Jun 25 19:14:58 CEST 2020
Hello Bin,
> -----Original Message-----
> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: Tuesday, June 23, 2020 11:00 AM
> To: Rick Chen <rick at andestech.com>; Simon Glass <sjg at chromium.org>;
> Pragnesh Patel <pragnesh.patel at sifive.com>; Sagar Kadam
> <sagar.kadam at sifive.com>; U-Boot Mailing List <u-boot at lists.denx.de>
> Cc: Bin Meng <bin.meng at windriver.com>
> Subject: [PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> From: Bin Meng <bin.meng at windriver.com>
>
> SYSRESET uclass driver already provides all the reset APIs, hence
> exclude our own ad-hoc reset.c implementation.
>
> Signed-off-by: Bin Meng <bin.meng at windriver.com>
> ---
>
> arch/riscv/lib/Makefile | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index b5e9324..6c503ff 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o
> obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> endif
> obj-y += interrupts.o
> +ifeq ($(CONFIG_$(SPL_)SYSRESET),)
> obj-y += reset.o
> +endif
I could see reset get's built when SYSRESET in enabled
CC spl/arch/riscv/lib/interrupts.o
CC spl/arch/riscv/lib/reset.o
AS spl/arch/riscv/lib/setjmp.o
Should this have been?
ifneq ($(CONFIG_$(SPL_)SYSRESET),)
Thanks & BR,
Sagar
> obj-y += setjmp.o
> obj-$(CONFIG_$(SPL_)SMP) += smp.o
> obj-$(CONFIG_SPL_BUILD) += spl.o
> --
> 2.7.4
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