[PATCH v3 11/15] board: ns3: define ddr memory layout
Simon Glass
sjg at chromium.org
Fri Jun 26 03:11:51 CEST 2020
Hi Rayagonda,
On Wed, 10 Jun 2020 at 04:42, Rayagonda Kokatanur
<rayagonda.kokatanur at broadcom.com> wrote:
>
> Add both DRAM banks memory information and
> the corresponding MMU page table mappings.
>
> Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty at broadcom.com>
> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
> ---
> arch/arm/dts/ns3-board.dts | 23 ++++++++++
> board/broadcom/bcmns3/ns3.c | 83 +++++++++++++++++++++++++++++++++++--
> configs/bcm_ns3_defconfig | 2 +
> 3 files changed, 105 insertions(+), 3 deletions(-)
>
Reviewed-by: Simon Glass <sjg at chromium.org>
nits below
> diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts
> index 54e56879a5..c660e74dc8 100644
> --- a/arch/arm/dts/ns3-board.dts
> +++ b/arch/arm/dts/ns3-board.dts
> @@ -5,6 +5,29 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/memory/bcm-ns3-mc.h>
> +
> +/*
> + * Single mem reserve region which includes the following:
> + * Components name Start Addr Size
> + * ------------------------------------------------
> + * GIC LPI tables 0x8AD7_0000 0x0009_0000
> + * Nitro FW 0x8AE0_0000 0x0020_0000
> + * Nitro Crash dump 0x8B00_0000 0x0200_0000
> + * OPTEE OS 0x8D00_0000 0x0200_0000
> + * BL31 services 0x8F00_0000 0x0010_0000
> + * Tmon 0x8F10_0000 0x0000_1000
> + * LPM/reserved 0x8F10_1000 0x0000_1000
> + * ATF to Bl33 info 0x8F10_2000 0x0000_1000
> + * ATF error logs 0x8F10_3000 0x0001_0000
> + * Error log parser 0x8F11_3000 0x0010_0000
> + */
> +
> +/memreserve/ BCM_NS3_MEM_RSVE_START BCM_NS3_MEM_RSVE_END;
> +
> +/* CRMU page tables */
> +/memreserve/ BCM_NS3_CRMU_PGT_START BCM_NS3_CRMU_PGT_SIZE;
> +
> #include "ns3.dtsi"
>
> / {
> diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
> index d4f374a7c6..85d097887e 100644
> --- a/board/broadcom/bcmns3/ns3.c
> +++ b/board/broadcom/bcmns3/ns3.c
> @@ -5,6 +5,7 @@
> */
>
> #include <common.h>
> +#include <fdt_support.h>
> #include <asm/io.h>
> #include <asm/gic.h>
> #include <asm/gic-v3.h>
> @@ -13,6 +14,8 @@
> #include <asm/arch-bcmns3/bl33_info.h>
> #include <dt-bindings/memory/bcm-ns3-mc.h>
>
> +#define BANK_OFFSET(bank) ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
> +
> static struct mm_region ns3_mem_map[] = {
> {
> .virt = 0x0UL,
> @@ -22,9 +25,15 @@ static struct mm_region ns3_mem_map[] = {
> PTE_BLOCK_NON_SHARE |
> PTE_BLOCK_PXN | PTE_BLOCK_UXN
> }, {
> - .virt = 0x80000000UL,
> - .phys = 0x80000000UL,
> - .size = 0x80000000UL,
> + .virt = BCM_NS3_MEM_START,
> + .phys = BCM_NS3_MEM_START,
> + .size = BCM_NS3_MEM_LEN,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + .virt = BCM_NS3_BANK_1_MEM_START,
> + .phys = BCM_NS3_BANK_1_MEM_START,
> + .size = BCM_NS3_BANK_1_MEM_LEN,
> .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> PTE_BLOCK_INNER_SHARE
> }, {
> @@ -43,6 +52,72 @@ DECLARE_GLOBAL_DATA_PTR;
> */
> struct bl33_info *bl33_info __section(".data");
>
> +/*
> + * Run modulo 256 checksum calculation and return the calculated checksum
> + */
> +static u8 checksum_calc(u8 *p, unsigned int len)
> +{
> + unsigned int i;
> + u8 chksum = 0;
> +
> + for (i = 0; i < len; i++)
> + chksum += p[i];
> +
> + return chksum;
> +}
> +
> +/*
> + * This function parses the memory layout informaion from a reserved area in
information
> + * DDR, and then fix up the FDT before passing it to Linux.
> + *
> + * In the case of error, do nothing and the default memory layout in DT will
> + * be used
> + */
> +static void mem_info_parse_fixup(void *fdt)
> +{
> + u32 *p32, sig, i, nr_banks;
> + u64 *p64;
> + u64 start[BCM_NS3_MAX_NR_BANKS];
> + u64 len[BCM_NS3_MAX_NR_BANKS];
> +
> + /* validate signature */
> + p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
Use a struct instead of ad-hoc pointer reading. Here I think you want
something like:
struct xxx_dram_hdr {
u32 sig;
struct xxx_dram_bank bank[MAX_BANKS];
};
> + sig = *p32;
> + if (sig != BCM_NS3_DDR_INFO_SIG) {
> + printf("DDR info signature 0x%x invalid\n", sig);
> + return;
Return error code
> + }
> +
> + /* run checksum test to validate data */
> + if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
> + printf("Checksum on DDR info failed\n");
> + return;
> + }
> +
> + /* parse information for each bank */
> + nr_banks = 0;
> + for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
> + /* skip banks with a length of zero */
> + p64 = (u64 *)BANK_OFFSET(i);
> + if (*(p64 + 1) == 0)
> + continue;
> +
> + start[i] = *p64;
> + len[i] = *(p64 + 1);
> +
> + printf("mem[%u] 0x%llx - 0x%llx\n", i, start[i],
> + start[i] + len[i] - 1);
> + nr_banks++;
> + }
> +
> + if (!nr_banks) {
> + printf("No DDR banks detected\n");
> + return;
> + }
> +
> + fdt_fixup_memory_banks(fdt, start, len, nr_banks);
Check error - this can fail.
> +}
> +
> int board_init(void)
> {
> if (bl33_info->version != BL33_INFO_VERSION)
> @@ -97,6 +172,8 @@ int ft_board_setup(void *fdt, bd_t *bd)
> {
> gic_lpi_tables_init(BCM_NS3_GIC_LPI_BASE, MAX_GIC_REDISTRIBUTORS);
>
> + mem_info_parse_fixup(fdt);
Check error.
> +
> return 0;
> }
> #endif /* CONFIG_OF_BOARD_SETUP */
> diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig
> index 040e753f9f..9adb44cb51 100644
> --- a/configs/bcm_ns3_defconfig
> +++ b/configs/bcm_ns3_defconfig
> @@ -4,6 +4,7 @@ CONFIG_TARGET_BCMNS3=y
> CONFIG_SYS_TEXT_BASE=0xFF000000
> CONFIG_ENV_SIZE=0x80000
> CONFIG_NR_DRAM_BANKS=2
> +CONFIG_OF_BOARD_SETUP=y
> CONFIG_LOGLEVEL=7
> CONFIG_SILENT_CONSOLE=y
> CONFIG_SILENT_U_BOOT_ONLY=y
> @@ -21,3 +22,4 @@ CONFIG_CLK=y
> CONFIG_CLK_CCF=y
> CONFIG_DM_SERIAL=y
> CONFIG_SYS_NS16550=y
> +CONFIG_SPL_OF_LIBFDT=y
> --
> 2.17.1
>
Regards,
Simon
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