ZynqMP boot: no messages from SPL other than "Debug uart enabled"
andras.g.major at gmail.com
Thu Mar 12 10:12:18 CET 2020
> the issue is likely related to incorrect DDR configuration.
> BSS and Malloc space are in DDR. >
> rev1.1 has different DDR sodimm module then rev1.0.
Thanks, this never occurred to me as Xilinx says to use rev1.0 software
for rev1.1 boards, so that's what I did.
> I have generated psu init from vivado 2019.2 for 1.1 revision and send
> it to mailing list. I didn't test it on hw but please test it and let me
I had already done that in the past (feed Vivado 2019.2 psu file into
u-boot), with no success. Unfortunately, your patch doesn't help
either, the behaviour is still exactly the same as before.
> Build it like this.
> export DEVICE_TREE="zynqmp-zcu102-rev1.1"
> make xilinx_zynqmp_virt_defconfig
> make -j
For some reason, that's no enough: I have to manually set
CONFIG_DEVICE_TREE because xilinx_zynqmp_virt_defconfig sets it wrong.
In any case, behaviour is exactly the same as before.
More information about the U-Boot