[PATCH v3 00/17] mtd: spi-nor-core: add xSPI Octal DTR support
jagan at amarulasolutions.com
Tue May 12 18:43:17 CEST 2020
On Mon, Mar 30, 2020 at 9:15 PM Pratyush Yadav <p.yadav at ti.com> wrote:
> This series adds support for octal DTR flashes in the spi-nor framework,
> and then adds hooks for the Cypress Semper flash which is an xSPI
> compliant Octal DTR flash.
> The Cadence QSPI controller driver is also updated to run in Octal DTR
> Tested on TI J721e EVM with 1-bit ECC on the Cypress flash on top of
> This series depends on .
>  cf. <20200224071051.19331-1-p.yadav at ti.com>
>  https://lists.denx.de/pipermail/u-boot/2020-February/401192.html
> Changes in v3:
> - Read 2 bytes in Octal DTR mode when reading SR and FSR to avoid
> tripping up controllers.
> - Use op->data.nbytes as a measure of whether the data phase exists or
> not. This fixes data buswidth not being updadted for SR and FSR reads
> because they keep data buffer as NULL when calling spi_nor_setup_op().
> - Add support for Micron mt35xu512aba to run in Octal DTR mode.
Do you have foot-print statistics for these changes? if yes can mark it here.
More information about the U-Boot