[PATCH v3 00/17] mtd: spi-nor-core: add xSPI Octal DTR support

[Pratyush Yadav]

On 12/05/20 10:13PM, Jagan Teki wrote:
> On Mon, Mar 30, 2020 at 9:15 PM Pratyush Yadav <p.yadav at ti.com> wrote:
> >
> > Hi,
> >
> > This series adds support for octal DTR flashes in the spi-nor framework,
> > and then adds hooks for the Cypress Semper flash which is an xSPI
> > compliant Octal DTR flash.
> >
> > The Cadence QSPI controller driver is also updated to run in Octal DTR
> > mode.
> >
> > Tested on TI J721e EVM with 1-bit ECC on the Cypress flash on top of
> > u-boot-ti/next.
> >
> > This series depends on [0].
> >
> > [0] cf. <20200224071051.19331-1-p.yadav at ti.com>
> > [0] https://lists.denx.de/pipermail/u-boot/2020-February/401192.html
> >
> > Changes in v3:
> > - Read 2 bytes in Octal DTR mode when reading SR and FSR to avoid
> >   tripping up controllers.
> > - Use op->data.nbytes as a measure of whether the data phase exists or
> >   not. This fixes data buswidth not being updadted for SR and FSR reads
> >   because they keep data buffer as NULL when calling spi_nor_setup_op().
> > - Add support for Micron mt35xu512aba to run in Octal DTR mode.
> 
> Do you have foot-print statistics for these changes? if yes can mark it here.

Do you mean binary size difference?

With these changes, the U-Boot binary is 830308 bytes. Without them it 
is 825260 bytes. That is a 5048 byte increase.

With these changes, the SPL binary weighs in at 605312 bytes. Without 
them it is 600488 bytes. That is a 4824 byte increase.

This is with both the Spansion and STMicro configs enabled. When I 
disable them I get the follwing data.

U-Boot:
With: 822644
Without: 819688
Difference: 2956

SPL:
With: 599218
Without: 596192
Difference: 3026
 

-- 
Regards,
Pratyush Yadav
Texas Instruments India