[PATCH v2 1/3] board: ls2080aqds: transition to DM_ETH

[Ioana Ciornei]

In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated.  Also, force the PCI devices to be enumerated at probe
time.

Signed-off-by: Ioana Ciornei <ioana.ciornei at nxp.com>
---
 board/freescale/ls2080aqds/eth.c        | 13 +++++++++++--
 board/freescale/ls2080aqds/ls2080aqds.c |  4 ++++
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index bbb70a859a1e..47f57d94b847 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -24,6 +24,8 @@
 
 #define MC_BOOT_ENV_VAR "mcinitcmd"
 
+#ifndef CONFIG_DM_ETH
+
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
@@ -889,9 +891,11 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
 	}
 }
 #endif
+#endif // !CONFIG_DM_ETH
 
 int board_eth_init(bd_t *bis)
 {
+#ifndef CONFIG_DM_ETH
 	int error;
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
@@ -970,8 +974,13 @@ int board_eth_init(bd_t *bis)
 			sgmii_configure_repeater(2);
 	}
 #endif
-	error = pci_eth_init(bis);
-	return error;
+#endif // !CONFIG_DM_ETH
+
+#ifdef CONFIG_DM_ETH
+	return 0;
+#else
+	return pci_eth_init(bis);
+#endif
 }
 
 #if defined(CONFIG_RESET_PHY_R)
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 4034bdee2842..1c91c5b7f052 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -251,6 +251,10 @@ int board_init(void)
 	ppa_init();
 #endif
 
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+	pci_init();
+#endif
+
 	return 0;
 }
 
-- 
2.17.1