[PATCH v3 0/7] riscv: Clean up timer drivers
Sean Anderson
seanga2 at gmail.com
Tue Sep 1 12:32:01 CEST 2020
This series cleans up the timer drivers in RISC-V and converts them to DM.
This series depends on [1]. This series needs to be tested! I have only tested
it on QEMU and the K210. Notably, this means that the HiFive and anything Andes
is completely untested. CI for this series is located at [2].
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=190862
[2] https://dev.azure.com/seanga2/u-boot/_build/results?buildId=4
Changes in v3:
- Don't initialize the IPI in spl_invoke_opensbi. Further testing has
revealed it to be unnecessary.
- Rebase
Changes in v2:
- Remove RISCV_RDTIME KConfig option
- Split Kendryte binding changes into their own commit
- Fix SiFive CLINT not getting tick-rate from rtcclk
Sean Anderson (7):
riscv: Rework riscv timer driver to only support S-mode
riscv: Rework Andes PLMT as a UCLASS_TIMER driver
riscv: Clean up initialization in Andes PLIC
riscv: Rework Sifive CLINT as UCLASS_TIMER driver
riscv: clk: Add CLINT clock to kendryte clock driver
riscv: Update Kendryte device tree for new CLINT driver
riscv: Update SiFive device tree for new CLINT driver
arch/riscv/Kconfig | 16 ----
arch/riscv/dts/ae350_32.dts | 1 +
arch/riscv/dts/ae350_64.dts | 1 +
arch/riscv/dts/fu540-c000-u-boot.dtsi | 8 +-
.../dts/hifive-unleashed-a00-u-boot.dtsi | 4 +
arch/riscv/dts/k210.dtsi | 9 +-
arch/riscv/include/asm/global_data.h | 3 -
arch/riscv/lib/Makefile | 1 -
arch/riscv/lib/andes_plic.c | 58 ++++++-------
arch/riscv/lib/andes_plmt.c | 42 +++++----
arch/riscv/lib/rdtime.c | 38 --------
arch/riscv/lib/sifive_clint.c | 87 ++++++++++++-------
drivers/clk/kendryte/clk.c | 4 +
drivers/ram/sifive/Kconfig | 2 +
drivers/timer/Kconfig | 6 +-
drivers/timer/riscv_timer.c | 39 +++++----
include/dt-bindings/clock/k210-sysctl.h | 1 +
17 files changed, 150 insertions(+), 170 deletions(-)
delete mode 100644 arch/riscv/lib/rdtime.c
--
2.28.0
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