[PATCH 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs"
Sean Anderson
seanga2 at gmail.com
Mon Sep 7 20:16:53 CEST 2020
Clearing MIP doesn't do anything. Whoops. The following commits should
tackle this problem in a more robust manner.
This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6.
Signed-off-by: Sean Anderson <seanga2 at gmail.com>
---
arch/riscv/cpu/start.S | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bf9fdf369b..e3222b1ea7 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -65,8 +65,6 @@ _start:
#else
li t0, SIE_SSIE
#endif
- /* Clear any pending IPIs */
- csrc MODE_PREFIX(ip), t0
csrs MODE_PREFIX(ie), t0
#endif
--
2.28.0
More information about the U-Boot
mailing list