[PATCH] RFC: tegra: xhci: Allocate from non-cached memory

[twarren at nvidia.com]

From: Tom Warren <twarren at nvidia.com>

This fixes the XHCI driver on T210 boards (TX1, Nano). I was seeing
that Set_Address wasn't completing, returning with a Context Parameter
error. Examining the slot context, etc. showed that the correct info was
there in RAM. Once I set 'dcache off' globally, it started working.
This patch was created to force the TRB, etc. allocation to be in
non-cached memory, which resulted in XHCI working on Nano/TX1 w/o the
need for a global dcache disable. Thierry Reding pointed to a similar
fix he'd done for the rtl6189 driver.

Sending this to the list for comment, as this should have affected other
XHCI implementations on other SoCs. Note that Tegra X1 (T210) has a
64-byte cache line size (64-bit ARMv8), and I do see the
flush_cache/inval_cache ARM code being called via
xhci_cache_flash/xhci_inval_cache.

Change-Id: I591fd232425bf444b93be3695ee639d528d6713b
Signed-off-by: Tom Warren <twarren at nvidia.com>
---
 drivers/usb/host/xhci-mem.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index ed649c0..d52fe6c 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -193,7 +193,11 @@ static void *xhci_malloc(unsigned int size)
 	void *ptr;
 	size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE);
 
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+	ptr = (void *)noncached_alloc(ALIGN(size, cacheline_size), cacheline_size);
+#else
 	ptr = memalign(cacheline_size, ALIGN(size, cacheline_size));
+#endif
 	BUG_ON(!ptr);
 	memset(ptr, '\0', size);
 
-- 
1.8.2.1.610.g562af5b