[PATCH] RFC: tegra: xhci: Allocate from non-cached memory

[Bin Meng]

Hi Tom,

On Sat, Sep 12, 2020 at 3:43 AM <twarren at nvidia.com> wrote:
>
> From: Tom Warren <twarren at nvidia.com>
>
> This fixes the XHCI driver on T210 boards (TX1, Nano). I was seeing
> that Set_Address wasn't completing, returning with a Context Parameter
> error. Examining the slot context, etc. showed that the correct info was
> there in RAM. Once I set 'dcache off' globally, it started working.
> This patch was created to force the TRB, etc. allocation to be in
> non-cached memory, which resulted in XHCI working on Nano/TX1 w/o the
> need for a global dcache disable. Thierry Reding pointed to a similar
> fix he'd done for the rtl6189 driver.
>
> Sending this to the list for comment, as this should have affected other
> XHCI implementations on other SoCs. Note that Tegra X1 (T210) has a
> 64-byte cache line size (64-bit ARMv8), and I do see the
> flush_cache/inval_cache ARM code being called via
> xhci_cache_flash/xhci_inval_cache.
>
> Change-Id: I591fd232425bf444b93be3695ee639d528d6713b
> Signed-off-by: Tom Warren <twarren at nvidia.com>
> ---
>  drivers/usb/host/xhci-mem.c | 4 ++++
>  1 file changed, 4 insertions(+)
>

There are some fixes recently in the xHCI codes. Could you please
retest to see if this works on TX1?

Regards,
Bin