[PATCH v8 00/28] mtd: spi-nor-core: add xSPI Octal DTR support

Sean Anderson seanga2 at gmail.com
Mon Apr 5 15:17:52 CEST 2021

On 4/5/21 3:43 AM, Pratyush Yadav wrote:
> On 02/04/21 06:28PM, Sean Anderson wrote:
>> On 4/1/21 3:31 PM, Pratyush Yadav wrote:
>>> Hi,
>>> This series adds support for octal DTR flashes in the SPI NOR framework,
>> As an overall question, is this the same as "DDR" mode?
> Sort of...
> DDR is "Double Data Rate" which implies that the "double" part only
> refers to the data phase. DTR is "Double Transfer Rate" which means the
> "double" part refers to all 3 (command, address, data) phases.
> The underlying concept is the same: transfer data twice per clock cycle.

Thanks. I have a datasheet which refers to DTR in the command, address,
and data phases as DDR, and I was wondering if it was the same idea.


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