[PATCH 1/2] riscv: board: Support Openpiton Soc
Tianrui Wei
tianrui-wei at outlook.com
Tue Apr 20 12:13:56 CEST 2021
Hi Bin,
Many thanks for taking you time to review our patch, will fix the things
you've mentioned.
> -----Original Message-----
> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: Tuesday, April 20, 2021 5:41 PM
> To: Tianrui Wei <tianrui-wei at outlook.com>
> Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Leo Yu-Chi Liang
> <ycliang at andestech.com>; Rick Chen <rick at andestech.com>; Pantelis
> Antoniou <panto at antoniou-consulting.com>
> Subject: Re: [PATCH 1/2] riscv: board: Support Openpiton Soc
>
> Hi Tianrui,
>
> On Tue, Apr 20, 2021 at 1:16 PM Tianrui Wei <tianrui-wei at outlook.com> wrote:
> >
> > From b8736bf498afc0d250228b0c29f1b402d0d58361 Mon Sep 17 00:00:00
> 2001
> > From: Tianrui Wei <tianrui-wei at outlook.com>
> > Date: Mon, 20 April 2021 13:03:25 +0800
> > Subject: [PATCH 1/2] riscv: board: Support Openpiton Soc
> >
> > This patch enables support for OpenPiton risc-v SoC on
>
> nits: risc-v => RISC-V
>
> > Digilent Genesys2 FPGA with dual cores configuration
> >
> > Signed-off-by: Tianrui Wei <tianrui-wei at outlook.com>
> > Acked-by: Jonathan Balkind <jbalkind at ucsb.edu>
> >
> > ---
> >
> > arch/riscv/Kconfig | 4 +
> > arch/riscv/dts/Makefile | 1 +
> > arch/riscv/dts/openpiton-riscv64.dts | 160 +++++++++++++++++++++
> > board/openpiton/riscv/Kconfig | 42 ++++++
> > board/openpiton/riscv/MAINTAINERS | 6 +
> > board/openpiton/riscv/Makefile | 5 +
> > board/openpiton/riscv/openpiton-riscv.c | 41 ++++++
> > configs/openpiton_riscv64_defconfig | 132 +++++++++++++++++
> > include/configs/openpiton-riscv.h | 58 ++++++++
> > 9 files changed, 449 insertions(+)
> > create mode 100644 arch/riscv/dts/openpiton-riscv64.dts
> > create mode 100644 board/openpiton/riscv/Kconfig create mode 100644
> > board/openpiton/riscv/MAINTAINERS create mode 100644
> > board/openpiton/riscv/Makefile create mode 100644
> > board/openpiton/riscv/openpiton-riscv.c
> > create mode 100644 configs/openpiton_riscv64_defconfig
> > create mode 100644 include/configs/openpiton-riscv.h
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index
> > 30b05408..79f2b0b9 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -23,6 +23,9 @@ config TARGET_SIFIVE_FU540 config
> > TARGET_SIPEED_MAIX
> > bool "Support Sipeed Maix Board"
> >
> > +config TARGET_OPENPITON_RISCV
> > + bool "Support riscv cores on openpiton SoC"
>
> What's the official board name for this?
Openpiton is an SoC generator targeting various FPGA dev boards, you
could see it at openpiton.org. So the official board name is OpenPiton.
>
> > +
> > endchoice
> >
> > config SYS_ICACHE_OFF
> > @@ -57,6 +60,7 @@ source "board/emulation/qemu-riscv/Kconfig"
> > source "board/microchip/mpfs_icicle/Kconfig"
> > source "board/sifive/fu540/Kconfig"
> > source "board/sipeed/maix/Kconfig"
> > +source "board/openpiton/riscv/Kconfig"
>
> nits: please keep it sorted
>
> >
> > # platform-specific options below
> > source "arch/riscv/cpu/ax25/Kconfig"
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index
> > 3a6f96c6..0eb8014b 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -3,6 +3,7 @@
> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > +dtb-$(CONFIG_TARGET_OPENPITON_RISCV) += openpiton-riscv64.dtb
>
> ditto
>
> >
> > targets += $(dtb-y)
> >
> > diff --git a/arch/riscv/dts/openpiton-riscv64.dts
> > b/arch/riscv/dts/openpiton-riscv64.dts
> > new file mode 100644
> > index 00000000..9ef8280e
> > --- /dev/null
> > +++ b/arch/riscv/dts/openpiton-riscv64.dts
> > @@ -0,0 +1,160 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2021 Tianrui Wei <tianrui-wei at outlook.com> */
> > +
> > +// This dts is for a dual core instance of OpenPiton+Ariane built //
> > +to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files // are
> > +automatically generated by the OpenPiton build system and // this
> > +configuration may not be what you need if your configuration // is
> > +different from the below.
>
> Please avoid using // for multi-line comment blocks
>
> > +
> > +/dts-v1/;
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + u-boot,dm-pre-reloc;
> > + compatible = "openpiton,ariane";
> > +
> > + chosen {
> > + u-boot,dm-pre-reloc;
> > + bootargs = "debug loglevel=9";
>
> Above two seem to be unnecessary
>
> > + stdout-path = "uart0:115200";
> > + };
> > +
> > + aliases {
> > + u-boot,dm-pre-reloc;
>
> This seems unnecessary
>
> > + console = &uart0;
> > + serial0 = &uart0;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + u-boot,dm-pre-reloc;
> > + timebase-frequency = <520835>;
> > +
> > + CPU0: cpu at 0 {
> > + clock-frequency = <66667000>;
> > + u-boot,dm-pre-reloc;
> > + device_type = "cpu";
> > + reg = <0>;
> > + status = "okay";
> > + compatible = "eth, ariane", "riscv";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + tlb-split;
> > + // HLIC - hart local interrupt controller
> > + CPU0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + compatible = "riscv,cpu-intc";
> > + };
> > + };
> > +
> > + CPU1: cpu at 1 {
> > + clock-frequency = <66667000>;
> > + u-boot,dm-pre-reloc;
> > + device_type = "cpu";
> > + reg = <1>;
> > + status = "okay";
> > + compatible = "eth, ariane", "riscv";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + tlb-split;
> > + // HLIC - hart local interrupt controller
> > + CPU1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + compatible = "riscv,cpu-intc";
> > + };
> > + };
> > +
> > + };
> > +
> > + memory at 80000000 {
> > + u-boot,dm-pre-reloc;
> > + device_type = "memory";
> > + reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
> > + };
> > +
> > + uart0: uart at fff0c2c000 {
>
> nits: the indentation level is incorrect
>
> > + u-boot,dm-pre-reloc;
> > + compatible = "ns16550";
> > + reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
> > + clock-frequency = <66667000>;
> > + current-speed = <115200>;
> > + interrupt-parent = <&PLIC0>;
> > + interrupts = <1>;
> > + reg-shift = <0>;
> > + // regs are spaced on 8 bit boundary
> > + };
> > +
> > + eth: ethernet at fff0d00000 {
> > + compatible = "xlnx,xps-ethernetlite-1.00.a";
> > + device_type = "network";
> > + reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >;
> > + interrupt-parent = <&PLIC0>;
> > + interrupts = <2>;
> > + local-mac-address = [ 00 18 3E 02 E3 E5 ];
> > + phy-handle = <&phy0>;
> > + xlnx,duplex = <0x1>;
> > + xlnx,include-global-buffers = <0x1>;
> > + xlnx,include-internal-loopback = <0x0>;
> > + xlnx,include-mdio = <0x1>;
> > + xlnx,rx-ping-pong = <0x1>;
> > + xlnx,s-axi-id-width = <0x1>;
> > + xlnx,tx-ping-pong = <0x1>;
> > + xlnx,use-internal = <0x0>;
> > + axi_ethernetlite_0_mdio: mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + phy0: phy at 1 {
> > + compatible = "ethernet-phy-id001C.C915";
> > + device_type = "ethernet-phy";
> > + reg = <1>;
> > + };
> > + };
> > + };
> > +
> > + debug-controller at fff1000000 {
> > + compatible = "riscv,debug-013";
> > + interrupts-extended = < &CPU0_intc 65535
> > + &CPU1_intc 65535 >;
> > + reg = < 0x000000ff 0xf1000000 0x00000000 0x00001000 >;
> > + reg-names = "control";
> > + };
> > +
> > + sdhci_0: sdhci at 0xf000000000 {
> > + u-boot,dm-pre-reloc;
> > + status = "okay";
> > + compatible = "openpiton,piton-mmc";
> > + reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
> > + };
> > + clint at fff1020000 {
> > + u-boot,dm-pre-reloc;
> > + compatible = "riscv,clint0";
>
> Please use "sifive,clint0" as "riscv,clint0" is considered legacy
>
> > + interrupts-extended = < &CPU0_intc 3
> > + &CPU0_intc 7
> > + &CPU1_intc 3
> > + &CPU1_intc 7 >;
> > + reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
> > + reg-names = "control";
> > + };
> > +
> > + PLIC0: plic at fff1100000 {
> > + u-boot,dm-pre-reloc;
> > + #address-cells = <0>;
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,plic0";
>
> Please use "sifive,plic-1.0.0"
>
> > + interrupt-controller;
> > + interrupts-extended = < &CPU0_intc 11
> > + &CPU0_intc 9
> > + &CPU1_intc 11
> > + &CPU1_intc 9 >;
> > + reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
> > + riscv,max-priority = <7>;
> > + riscv,ndev = <2>;
> > + };
> > +
> > +};
> > +
> > diff --git a/board/openpiton/riscv/Kconfig
> > b/board/openpiton/riscv/Kconfig new file mode 100644 index
> > 00000000..31ae44d5
> > --- /dev/null
> > +++ b/board/openpiton/riscv/Kconfig
> > @@ -0,0 +1,42 @@
> > +if TARGET_OPENPITON_RISCV
> > +
> > +config SYS_BOARD
> > + default "riscv"
> > +
> > +config SYS_VENDOR
> > + default "openpiton"
> > +
> > +config SYS_CPU
> > + default "generic"
> > +
> > +config SYS_CONFIG_NAME
> > + default "openpiton-riscv"
> > +
> > +config SYS_TEXT_BASE
> > + default 0x81000000 if SPL
> > + default 0x80000000 if !RISCV_SMODE
> > + default 0x81000000 if RISCV_SMODE
> > +
> > +config SPL_TEXT_BASE
> > + default 0x80000000
> > +
> > +config SPL_OPENSBI_LOAD_ADDR
> > + default 0x81000000
> > +
> > +config BOARD_SPECIFIC_OPTIONS # dummy
> > + def_bool y
> > + select ARCH_EARLY_INIT_R
> > + select SUPPORT_SPL
> > + imply CPU_RISCV
> > + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
> > + imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
> > + imply CMD_CPU
> > + imply SPL_CPU_SUPPORT
> > + imply SPL_OPENSBI
> > + imply SPL_LOAD_FIT
> > + imply SPL_SMP
> > + imply SPL_MMC
> > + imply SMP
> > + imply SPL_RISCV_MMODE
> > +
> > +endif
> > diff --git a/board/openpiton/riscv/MAINTAINERS
> > b/board/openpiton/riscv/MAINTAINERS
> > new file mode 100644
> > index 00000000..1db6fb60
> > --- /dev/null
> > +++ b/board/openpiton/riscv/MAINTAINERS
> > @@ -0,0 +1,6 @@
> > +Openpiton Riscv Bootloader
> > +M: Tianrui Wei<tianrui-wei at outlook.com>
> > +S: Maintained
> > +F: board/openpiton/riscv/
> > +F: include/configs/openpiton-riscv.h
> > +F: configs/openpiton_riscv_defconfig
> > diff --git a/board/openpiton/riscv/Makefile
> > b/board/openpiton/riscv/Makefile new file mode 100644 index
> > 00000000..8cc20e7c
> > --- /dev/null
> > +++ b/board/openpiton/riscv/Makefile
> > @@ -0,0 +1,5 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (C) 2021 Tianrui Wei
> > +# Tianrui Wei <tianrui-wei at outlook.com> obj-y += openpiton-riscv.o
> > diff --git a/board/openpiton/riscv/openpiton-riscv.c
> > b/board/openpiton/riscv/openpiton-riscv.c
> > new file mode 100644
> > index 00000000..5be407e7
> > --- /dev/null
> > +++ b/board/openpiton/riscv/openpiton-riscv.c
> > @@ -0,0 +1,41 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2019 SiFive, Inc
> > + * Copyright (c) 2021 Tianrui Wei
> > + *
> > + *
> > + * Authors:
> > + * Pragnesh Patel <pragnesh.patel at sifive.com>
> > + * Tianrui Wei <tianrui-wei at outlook.com>
> > + */
> > +#include <common.h>
> > +#include <init.h>
> > +#include <configs/openpiton-riscv.h>
> > +#include <dm.h>
> > +#include <spl.h>
> > +
> > +#ifdef CONFIG_SPL
> > +void board_boot_order(u32 *spl_boot_list) {
> > + u8 i;
> > + u32 boot_devices[] = {
> > + BOOT_DEVICE_MMC1,
> > + };
> > +
> > + for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
> > + spl_boot_list[i] = boot_devices[i]; } #endif
> > +
> > +#ifdef CONFIG_SPL_LOAD_FIT
> > +int board_fit_config_name_match(const char *name) {
> > + /* boot using first FIT config */
> > + return 0;
> > +}
> > +#endif
> > +
> > +int board_init(void)
> > +{
> > + return 0;
> > +}
> > diff --git a/configs/openpiton_riscv64_defconfig
> > b/configs/openpiton_riscv64_defconfig
> > new file mode 100644
> > index 00000000..37aa3c80
> > --- /dev/null
> > +++ b/configs/openpiton_riscv64_defconfig
> > @@ -0,0 +1,132 @@
> > +CONFIG_RISCV=y
> > +CONFIG_NR_DRAM_BANKS=1
> > +CONFIG_SPL=y
> > +CONFIG_SPL_MMC_SUPPORT=y
> > +CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
> > +CONFIG_TARGET_OPENPITON_RISCV=y
> > +CONFIG_ARCH_RV64I=y
> > +CONFIG_RISCV_SMODE=y
> > +CONFIG_MISC_INIT_R=n
> > +CONFIG_SYS_MALLOC_F_LEN=0x1000
> > +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
> > +CONFIG_SPL_PAYLOAD=""
> > +CONFIG_LIBDISK_SUPPORT=y
> > +CONFIG_NR_CPUS=32
> > +CONFIG_CMODEL_MEDANY=y
> > +CONFIG_EXPORT=n
> > +CONFIG_HASH=n
> > +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > +CONFIG_SPL_BANNER_PRINT=n
> > +CONFIG_SPL_CRC32_SUPPORT=n
> > +CONFIG_GENERATE_SMBIOS_TABLE=n
> > +CONFIG_EFI_LOADER=n
> > +CONFIG_LIB_DATA=y
> > +CONFIG_SPL_USE_TINY_PRINTF=y
> > +CONFIG_SPL_TINY_MEMSET=y
> > +CONFIG_FS_EXT4=y
> > +CONFIG_DM_RTC=y
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_SPL_OPENSBI=n
> > +CONFIG_SPL_RTC_SUPPORT=y
> > +CONFIG_SPL_FS_EXT4=y
> > +CONFIG_SPL_LEGACY_IMAGE_SUPPORT=n
> > +CONFIG_CMD_NET=n
> > +CONFIG_EFI_PARTITION=y
> > +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=128
> > +CONFIG_EFI_PARTITION_ENTRIES_OFF=0
> > +CONFIG_SPL_EFI_PARTITION=y
> > +CONFIG_PARTITION_UUIDS=y
> > +CONFIG_OF_EMBED=y
> > +CONFIG_HAVE_BLOCK_DEVICE=y
> > +CONFIG_CPU=y
> > +CONFIG_CPU_RISCV=y
> > +CONFIG_MMC=y
> > +CONFIG_DM_MMC=y
> > +CONFIG_SPL_DM_MMC=y
> > +CONFIG_MMC_PITON=y
> > +CONFIG_MMC_QUIRKS=y
> > +CONFIG_DEBUG_UART=y
> > +CONFIG_DEBUG_UART_NS16550=y
> > +CONFIG_DEBUG_UART_SHIFT=0
> > +CONFIG_DEBUG_UART_ANNOUNCE=y
> > +CONFIG_DEBUG_UART_SKIP_INIT=y
> > +CONFIG_DEBUG_UART_BASE=0xfff0c2c000
> > +CONFIG_DEBUG_UART_CLOCK=66667000
> > +CONFIG_SPL_LIBDISK_SUPPORT=y
> > +CONFIG_MMC_VERBOSE=n
> > +CONFIG_MMC_WRITE=n
> > +CONFIG_MMC_HW_PARTITIONING=n
> > +CONFIG_SYS_RELOC_GD_ENV_ADDR=n
> > +CONFIG_SAVEENV=n
> > +CONFIG_NET=n
> > +CONFIG_SPL_PARTITION_UUIDS=n
> > +CONFIG_CMD_EXT4=y
> > +CONFIG_CMD_FS_GENERIC=y
> > +CONFIG_CMD_READ=y
> > +CONFIG_CMD_LSBLK=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_GPT=y
> > +CONFIG_CMD_MEMINFO=y
> > +CONFIG_EXPERT=n
> > +CONFIG_ENV_VARS_UBOOT_CONFIG=y
> > +CONFIG_LEGACY_IMAGE_FORMAT=n
> > +CONFIG_ARCH_FIXUP_FDT_MEMORY=n
> > +CONFIG_MENU=y
> > +CONFIG_CMD_BOOTZ=y
> > +CONFIG_CMD_PART=y
> > +CONFIG_SHOW_REGS=y
> > +CONFIG_LOG=y
> > +CONFIG_LOGLEVEL=9
> > +CONFIG_SPL_LOGLEVEL=9
> > +CONFIG_TPL_LOGLEVEL=9
> > +CONFIG_SPL_LOG=y
> > +CONFIG_SPL_LOG_MAX_LEVEL=9
> > +CONFIG_SPL_LOG_CONSOLE=y
> > +CONFIG_LOG_ERROR_RETURN=y
> > +CONFIG_CMD_CPU=n
> > +CONFIG_BOOTM_NETBSD=n
> > +CONFIG_BOOTM_PLAN9=n
> > +CONFIG_BOOTM_RTEMS=n
> > +CONFIG_BOOTM_VXWORKS=n
> > +CONFIG_CMD_RUN=n
> > +CONFIG_CMD_IMI=n
> > +CONFIG_CMD_XIMG=n
> > +CONFIG_CMD_EXPORTENV=n
> > +CONFIG_CMD_IMPORTENV=n
> > +CONFIG_CMD_EDITENV=n
> > +CONFIG_CMD_SAVEENV=n
> > +CONFIG_CMD_CRC32=n
> > +CONFIG_CMD_RANDOM=n
> > +CONFIG_CMD_LZMADEC=n
> > +CONFIG_CMD_UNLZ4=n
> > +CONFIG_CMD_UNZIP=n
> > +CONFIG_CMD_FLASH=n
> > +CONFIG_RANDOM_UUID=n
> > +CONFIG_CMD_LOADB=n
> > +CONFIG_CMD_LOADS=n
> > +CONFIG_CMD_ECHO=n
> > +CONFIG_CMD_ITEST=n
> > +CONFIG_CMD_SOURCE=n
> > +CONFIG_CMD_SETEXPR=n
> > +CONFIG_CMD_BLOCK_CACHE=n
> > +CONFIG_CMD_DATE=n
> > +CONFIG_CMD_SLEEP=n
> > +CONFIG_CMD_SYSBOOT=y
> > +CONFIG_CMD_FAT=y
> > +CONFIG_DOS_PARTITION=y
> > +CONFIG_ISO_PARTITION=y
> > +CONFIG_DM_ETH=y
> > +CONFIG_RAM=y
> > +CONFIG_SPL_RAM=y
> > +CONFIG_FS_FAT=y
> > +CONFIG_FS_FAT_MAX_CLUSTSIZE=65536
> > +CONFIG_FS_SQUASHFS=y
> > +CONFIG_SHA1=y
> > +CONFIG_SHA256=y
> > +CONFIG_MD5=y
> > +CONFIG_ZLIB_UNCOMPRESS=y
> > +CONFIG_SPL_GZIP=y
> > +CONFIG_SPL_ZLIB=y
> > +CONFIG_GETOPT=y
> > +CONFIG_OF_LIBFDT_OVERLAY=y
> > +CONFIG_RAM_SIFIVE=n
> > diff --git a/include/configs/openpiton-riscv.h
> > b/include/configs/openpiton-riscv.h
> > new file mode 100644
> > index 00000000..0f30609b
> > --- /dev/null
> > +++ b/include/configs/openpiton-riscv.h
> > @@ -0,0 +1,58 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> > + * Copyright (c) 2021 Tianrui Wei
> > + *
> > + * Authors:
> > + * Anup Patel <anup.patel at wdc.com>
> > + * Tianrui Wei <tianrui-wei at outlook.com>
> > + */
> > +
> > +#ifndef __OPENPITON_RISCV_CONFIG_H
> > +#define __OPENPITON_RISCV_CONFIG_H
> > +
> > +#include <linux/sizes.h>
> > +#define DEBUG
> > +#ifdef CONFIG_SPL
> > +#define CONFIG_SPL_MAX_SIZE 0x00100000
> > +#define CONFIG_SPL_BSS_START_ADDR 0x82000000
> > +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
> > +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR
> + \
> > + CONFIG_SPL_BSS_MAX_SIZE) #define
> > +CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000
> > +#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \
> > + GENERATED_GBL_DATA_SIZE)
> > +
> > +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin"
> > +#define CONFIG_SPL_GD_ADDR 0x85000000 #endif
> > +
> > +/* Environment options */
> > +#define CONFIG_SYS_SDRAM_BASE 0x80000000
> > +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
> > +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
> > +#define CONFIG_SYS_MALLOC_LEN SZ_256M
> > +#define CONFIG_SYS_BOOTM_LEN SZ_256M
> > +
> > +/* -------------------------------------------------
> > + * Environment
> > + */
> > +//Disable persistent environment variable storage
> > +#define CONFIG_ENV_IS_NOWHERE 1
> > +
> > +/*
> > +---------------------------------------------------------------------
> > + * Board boot configuration
> > + */
> > +
> > +#define CONFIG_EXTRA_ENV_SETTINGS "\0"
> > +
> > +#define CONFIG_USE_BOOTCOMMAND
> > +#define CONFIG_BOOTCOMMAND \
> > + "fdt addr ${fdtcontroladdr}; " \
> > + "fdt move ${fdtcontroladdr} 0x86000000; " \
> > + "ext4load mmc 0:1 0x80200000 boot/Image; " \
> > + "booti 0x80200000 - 0x86000000; "
> > +
> > +#define CONFIG_TIMESTAMP /* Print image info with timestamp */
> > +
> > +#endif/* __CONFIG_H */
> > --
>
> Please add a documentation to describe related information of this board in
> doc/board/
>
> Regards,
> Bin
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