Question/issues about i.MX6 DDR configuration

[Fabio Estevam]

Hi Michael,

On Thu, Dec 2, 2021 at 5:36 PM Michael Nazzareno Trimarchi
<michael at amarulasolutions.com> wrote:

> The bootrom loads the dcd using some logic and you write the register
> in sequence.
> You don't respect the ddr initialization or this delay on MMDC
> according to 44.4.2.
> Is that not necessary?

I don't see in 44.4.2 where it mentions the requirement of delay
between register writes.

The part that Francesco quoted:

"A Precharge All command must be issued prior to the
MRW command to ensure robust DDR initialization. This
command is required to be issued to both chip selects if two
chip selects are utilized in the system."

Does not apply to mx6sabresd as it only has one chip select.

Regards,

Fabio Estevam