[PATCH v2] spi: zynqmp_gqspi: support dual and quad mode

Ashok Reddy Soma ashokred at xilinx.com
Wed Feb 3 13:16:20 CET 2021


Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma at xilinx.com>

> -----Original Message-----
> From: Brandon Maier <brandon.maier at rockwellcollins.com>
> Sent: Wednesday, January 20, 2021 10:10 PM
> To: u-boot at lists.denx.de
> Cc: bmeng.cn at gmail.com; Brandon Maier
> <brandon.maier at rockwellcollins.com>; jagan at amarulasolutions.com; Michal
> Simek <michals at xilinx.com>; Ashok Reddy Soma <ashokred at xilinx.com>
> Subject: [PATCH v2] spi: zynqmp_gqspi: support dual and quad mode
> 
> The dm_spi_ops.xfer() API does not support dual and quad SPI modes. It also
> doesn't allow the zynqmp_gqspi driver to calculate the correct number of
> dummy cycles for some NOR ops (as doing so also requires the buswidth).
> 
> Port the zynqmp_gqspi driver to spi_controller_mem_ops, which gives us the
> buswidth values to correctly support all SNOR_PROTO_X_X_X commands and to
> properly calculate dummy cycles.
> 
> Signed-off-by: Brandon Maier <brandon.maier at rockwellcollins.com>
> CC: jagan at amarulasolutions.com
> CC: michal.simek at xilinx.com
> CC: Ashok Reddy Soma <ashokred at xilinx.com>
> ---
> v1: https://lists.denx.de/pipermail/u-boot/2021-January/437506.html
> 
> v2:
> - Initialize 'ret' to 0 for exec_op() commands without data in/out.
> ---
>  drivers/spi/zynqmp_gqspi.c | 164 ++++++++++++++++---------------------
>  1 file changed, 70 insertions(+), 94 deletions(-)
> 
> diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index
> efcbd0557f..c7db43a09a 100644
> --- a/drivers/spi/zynqmp_gqspi.c
> +++ b/drivers/spi/zynqmp_gqspi.c
> @@ -16,6 +16,7 @@
>  #include <malloc.h>
>  #include <memalign.h>
>  #include <spi.h>
> +#include <spi-mem.h>
>  #include <ubi_uboot.h>
>  #include <wait_bit.h>
>  #include <dm/device_compat.h>
> @@ -171,8 +172,7 @@ struct zynqmp_qspi_priv {
>  	unsigned int len;
>  	int bytes_to_transfer;
>  	int bytes_to_receive;
> -	unsigned int is_inst;
> -	unsigned int cs_change:1;
> +	const struct spi_mem_op *op;
>  };
> 
>  static int zynqmp_qspi_of_to_plat(struct udevice *bus) @@ -221,6 +221,21
> @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
>  	return gqspi_fifo_reg;
>  }
> 
> +static u32 zynqmp_qspi_genfifo_mode(u8 buswidth) {
> +	switch (buswidth) {
> +	case 1:
> +		return GQSPI_SPI_MODE_SPI;
> +	case 2:
> +		return GQSPI_SPI_MODE_DUAL_SPI;
> +	case 4:
> +		return GQSPI_SPI_MODE_QSPI;
> +	default:
> +		debug("Unsupported bus width %u\n", buswidth);
> +		return GQSPI_SPI_MODE_SPI;
> +	}
> +}
> +
>  static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
>  				      u32 gqspi_fifo_reg)
>  {
> @@ -445,21 +460,42 @@ static int zynqmp_qspi_fill_tx_fifo(struct
> zynqmp_qspi_priv *priv, u32 size)
> 
>  static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)  {
> +	const struct spi_mem_op *op = priv->op;
>  	u32 gen_fifo_cmd;
> -	u32 bytecount = 0;
> +	u8 i, dummy_cycles, addr;
> +
> +	/* Send opcode */
> +	gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> +	gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
> +	gen_fifo_cmd |= GQSPI_GFIFO_TX;
> +	gen_fifo_cmd |= op->cmd.opcode;
> +	zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
> +
> +	/* Send address */
> +	for (i = 0; i < op->addr.nbytes; i++) {
> +		addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
> 
> -	while (priv->len) {
>  		gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> -		gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI;
> -		gen_fifo_cmd |= *(u8 *)priv->tx_buf;
> -		bytecount++;
> -		priv->len--;
> -		priv->tx_buf = (u8 *)priv->tx_buf + 1;
> +		gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op-
> >addr.buswidth);
> +		gen_fifo_cmd |= GQSPI_GFIFO_TX;
> +		gen_fifo_cmd |= addr;
> 
>  		debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
> 
>  		zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
>  	}
> +
> +	/* Send dummy */
> +	if (op->dummy.nbytes) {
> +		dummy_cycles = op->dummy.nbytes * 8 / op-
> >dummy.buswidth;
> +
> +		gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> +		gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op-
> >dummy.buswidth);
> +		gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX);
> +		gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK;
> +		gen_fifo_cmd |= dummy_cycles;
> +		zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
> +	}
>  }
> 
>  static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv, @@ -496,11
> +532,10 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv
> *priv)
>  	int ret = 0;
> 
>  	gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> +	gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op-
> >data.buswidth);
>  	gen_fifo_cmd |= GQSPI_GFIFO_TX |
>  			GQSPI_GFIFO_DATA_XFR_MASK;
> 
> -	gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
> -
>  	while (priv->len) {
>  		len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
>  		zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); @@ -574,11
> +609,10 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv
> *priv)
>  	u32 actuallen = priv->len;
> 
>  	gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> +	gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op-
> >data.buswidth);
>  	gen_fifo_cmd |= GQSPI_GFIFO_RX |
>  			GQSPI_GFIFO_DATA_XFR_MASK;
> 
> -	gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
> -
>  	/*
>  	 * Check if receive buffer is aligned to 4 byte and length
>  	 * is multiples of four byte as we are using dma to receive.
> @@ -595,62 +629,6 @@ static int zynqmp_qspi_genfifo_fill_rx(struct
> zynqmp_qspi_priv *priv)
>  	return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);  }
> 
> -static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv) -{
> -	int ret = 0;
> -
> -	if (priv->is_inst) {
> -		if (priv->tx_buf)
> -			zynqmp_qspi_genfifo_cmd(priv);
> -		else
> -			return -EINVAL;
> -	} else {
> -		if (priv->tx_buf)
> -			ret = zynqmp_qspi_genfifo_fill_tx(priv);
> -		else if (priv->rx_buf)
> -			ret = zynqmp_qspi_genfifo_fill_rx(priv);
> -		else
> -			return -EINVAL;
> -	}
> -	return ret;
> -}
> -
> -static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv) -{
> -	static unsigned int cs_change = 1;
> -	int status = 0;
> -
> -	debug("%s\n", __func__);
> -
> -	while (1) {
> -		/* Select the chip if required */
> -		if (cs_change)
> -			zynqmp_qspi_chipselect(priv, 1);
> -
> -		cs_change = priv->cs_change;
> -
> -		if (!priv->tx_buf && !priv->rx_buf && priv->len) {
> -			status = -EINVAL;
> -			break;
> -		}
> -
> -		/* Request the transfer */
> -		if (priv->len) {
> -			status = zynqmp_qspi_start_transfer(priv);
> -			priv->is_inst = 0;
> -			if (status < 0)
> -				break;
> -		}
> -
> -		if (cs_change)
> -			/* Deselect the chip */
> -			zynqmp_qspi_chipselect(priv, 0);
> -		break;
> -	}
> -
> -	return status;
> -}
> -
>  static int zynqmp_qspi_claim_bus(struct udevice *dev)  {
>  	struct udevice *bus = dev->parent;
> @@ -673,45 +651,43 @@ static int zynqmp_qspi_release_bus(struct udevice
> *dev)
>  	return 0;
>  }
> 
> -int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void
> *dout,
> -		     void *din, unsigned long flags)
> +static int zynqmp_qspi_exec_op(struct spi_slave *slave,
> +			       const struct spi_mem_op *op)
>  {
> -	struct udevice *bus = dev->parent;
> -	struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
> +	struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent);
> +	int ret = 0;
> 
> -	debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
> -	      (unsigned long)priv, bitlen, (unsigned long)dout);
> -	debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
> +	priv->op = op;
> +	priv->tx_buf = op->data.buf.out;
> +	priv->rx_buf = op->data.buf.in;
> +	priv->len = op->data.nbytes;
> 
> -	priv->tx_buf = dout;
> -	priv->rx_buf = din;
> -	priv->len = bitlen / 8;
> +	zynqmp_qspi_chipselect(priv, 1);
> 
> -	/*
> -	 * Assume that the beginning of a transfer with bits to
> -	 * transmit must contain a device command.
> -	 */
> -	if (dout && flags & SPI_XFER_BEGIN)
> -		priv->is_inst = 1;
> -	else
> -		priv->is_inst = 0;
> +	/* Send opcode, addr, dummy */
> +	zynqmp_qspi_genfifo_cmd(priv);
> 
> -	if (flags & SPI_XFER_END)
> -		priv->cs_change = 1;
> -	else
> -		priv->cs_change = 0;
> +	/* Request the transfer */
> +	if (op->data.dir == SPI_MEM_DATA_IN)
> +		ret = zynqmp_qspi_genfifo_fill_rx(priv);
> +	else if (op->data.dir == SPI_MEM_DATA_OUT)
> +		ret = zynqmp_qspi_genfifo_fill_tx(priv);
> 
> -	zynqmp_qspi_transfer(priv);
> +	zynqmp_qspi_chipselect(priv, 0);
> 
> -	return 0;
> +	return ret;
>  }
> 
> +static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
> +	.exec_op = zynqmp_qspi_exec_op,
> +};
> +
>  static const struct dm_spi_ops zynqmp_qspi_ops = {
>  	.claim_bus      = zynqmp_qspi_claim_bus,
>  	.release_bus    = zynqmp_qspi_release_bus,
> -	.xfer           = zynqmp_qspi_xfer,
>  	.set_speed      = zynqmp_qspi_set_speed,
>  	.set_mode       = zynqmp_qspi_set_mode,
> +	.mem_ops        = &zynqmp_qspi_mem_ops,
>  };
> 
>  static const struct udevice_id zynqmp_qspi_ids[] = {
> --
> 2.29.1



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