[PATCH v2] spi: zynqmp_gqspi: support dual and quad mode

[Michal Simek]

On 2/3/21 1:31 PM, Bin Meng wrote:
> On Thu, Jan 21, 2021 at 12:40 AM Brandon Maier
> <brandon.maier at rockwellcollins.com> wrote:
>>
>> The dm_spi_ops.xfer() API does not support dual and quad SPI modes. It
>> also doesn't allow the zynqmp_gqspi driver to calculate the correct
>> number of dummy cycles for some NOR ops (as doing so also requires the
>> buswidth).
>>
>> Port the zynqmp_gqspi driver to spi_controller_mem_ops, which gives us
>> the buswidth values to correctly support all SNOR_PROTO_X_X_X commands
>> and to properly calculate dummy cycles.
>>
>> Signed-off-by: Brandon Maier <brandon.maier at rockwellcollins.com>
>> CC: jagan at amarulasolutions.com
>> CC: michal.simek at xilinx.com
>> CC: Ashok Reddy Soma <ashokred at xilinx.com>
>> ---
>> v1: https://lists.denx.de/pipermail/u-boot/2021-January/437506.html
>>
>> v2:
>> - Initialize 'ret' to 0 for exec_op() commands without data in/out.
>> ---
>>  drivers/spi/zynqmp_gqspi.c | 164 ++++++++++++++++---------------------
>>  1 file changed, 70 insertions(+), 94 deletions(-)
>>
> 
> Reviewed-by: Bin Meng <bin.meng at windriver.com>
> 

Just wanted to reply that I have added your tag there you gave in v1.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs