[PATCH 05/25] arm: imx: Remove MX23 support

Stefano Babic sbabic at denx.de
Tue Feb 9 17:15:33 CET 2021


On 09.02.21 14:02, Tom Rini wrote:
> As there are now no boards for the MX23 family, remove the general
> support.
> 

I am fine to drop it.

Acked-by: Stefano Babic <sbabic at denx.de>

Best regards,
Stefano


> Cc: Stefano Babic <sbabic at denx.de>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: NXP i.MX U-Boot Team <uboot-imx at nxp.com>
> Signed-off-by: Tom Rini <trini at konsulko.com>
> ---
>  arch/arm/Kconfig                              |   8 +-
>  arch/arm/Makefile                             |   2 +-
>  arch/arm/cpu/arm926ejs/mxs/Makefile           |   1 -
>  arch/arm/cpu/arm926ejs/mxs/clock.c            |  31 +-
>  arch/arm/cpu/arm926ejs/mxs/iomux.c            |   7 +-
>  .../cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg   |   5 -
>  arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg  |   7 -
>  arch/arm/cpu/arm926ejs/mxs/spl_boot.c         |  31 +-
>  arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c     |  85 +----
>  arch/arm/cpu/arm926ejs/mxs/spl_power_init.c   |  50 +--
>  arch/arm/cpu/arm926ejs/mxs/timer.c            |  12 +-
>  arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd    |  18 -
>  arch/arm/include/asm/arch-mxs/imx-regs.h      |   5 -
>  arch/arm/include/asm/arch-mxs/iomux-mx23.h    | 349 ------------------
>  arch/arm/include/asm/arch-mxs/regs-base.h     |  46 +--
>  .../include/asm/arch-mxs/regs-clkctrl-mx23.h  | 209 -----------
>  .../include/asm/arch-mxs/regs-power-mx23.h    | 344 -----------------
>  arch/arm/include/asm/arch-mxs/regs-ssp.h      |  42 +--
>  arch/arm/include/asm/arch-mxs/regs-timrot.h   |  97 +----
>  arch/arm/include/asm/arch-mxs/sys_proto.h     |  17 +-
>  arch/arm/include/asm/mach-imx/dma.h           |  14 +-
>  arch/arm/include/asm/mach-imx/regs-apbh.h     | 115 +-----
>  arch/arm/include/asm/mach-imx/regs-lcdif.h    |  12 -
>  arch/arm/mach-imx/mxs/Kconfig                 |  21 --
>  drivers/dma/apbh_dma.c                        |   5 +-
>  drivers/gpio/mxs_gpio.c                       |  12 +-
>  drivers/mmc/mxsmmc.c                          |  12 +-
>  drivers/spi/mxs_spi.c                         |   9 +-
>  include/configs/mxs.h                         |  14 +-
>  tools/Makefile                                |   5 +-
>  30 files changed, 44 insertions(+), 1541 deletions(-)
>  delete mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg
>  delete mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
>  delete mode 100644 arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
>  delete mode 100644 arch/arm/include/asm/arch-mxs/iomux-mx23.h
>  delete mode 100644 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
>  delete mode 100644 arch/arm/include/asm/arch-mxs/regs-power-mx23.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 95557d6ed6bd..f2a87c3caed8 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -856,12 +856,6 @@ config ARCH_IMXRT
>  	select SUPPORT_SPL
>  	imply CMD_DM
>  
> -config ARCH_MX23
> -	bool "NXP i.MX23 family"
> -	select CPU_ARM926EJS
> -	select PL011_SERIAL
> -	select SUPPORT_SPL
> -
>  config ARCH_MX25
>  	bool "NXP MX25"
>  	select CPU_ARM926EJS
> @@ -2042,6 +2036,6 @@ source "arch/arm/Kconfig.debug"
>  endmenu
>  
>  config SPL_LDSCRIPT
> -	default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
> +	default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if ARCH_MX28 && !SPL_FRAMEWORK
>  	default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
>  	default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 28b523b37c70..7c1bca7f9269 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -107,7 +107,7 @@ libs-y += arch/arm/cpu/
>  libs-y += arch/arm/lib/
>  
>  ifeq ($(CONFIG_SPL_BUILD),y)
> -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
> +ifneq (,$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
>  libs-y += arch/arm/mach-imx/
>  endif
>  else
> diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
> index f60e61e4343f..f846a5400a3d 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/Makefile
> +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
> @@ -12,7 +12,6 @@ obj-y	+= spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
>  endif
>  
>  # Specify the target for use in elftosb call
> -MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx23.cfg
>  MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg
>  
>  # Generate HAB-capable IVT
> diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
> index 4e1cf3a1e32b..9aa6f83bb395 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/clock.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
> @@ -28,9 +28,7 @@
>  #define	PLL_FREQ_MHZ	(PLL_FREQ_KHZ / 1000)
>  #define	XTAL_FREQ_MHZ	(XTAL_FREQ_KHZ / 1000)
>  
> -#if defined(CONFIG_MX23)
> -#define MXC_SSPCLK_MAX MXC_SSPCLK0
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define MXC_SSPCLK_MAX MXC_SSPCLK3
>  #endif
>  
> @@ -113,10 +111,7 @@ static uint32_t mxs_get_gpmiclk(void)
>  {
>  	struct mxs_clkctrl_regs *clkctrl_regs =
>  		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
> -#if defined(CONFIG_MX23)
> -	uint8_t *reg =
> -		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	uint8_t *reg =
>  		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
>  #endif
> @@ -319,9 +314,7 @@ void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq)
>  	if (freq == 0)
>  		return;
>  
> -#if defined(CONFIG_MX23)
> -	writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
>  #endif
>  
> @@ -367,23 +360,7 @@ void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq)
>  
>  	k_best /= 1000;
>  
> -#if defined(CONFIG_MX23)
> -	writeb(CLKCTRL_FRAC_CLKGATE,
> -		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
> -	writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
> -		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
> -	writeb(CLKCTRL_FRAC_CLKGATE,
> -		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
> -
> -	writel(CLKCTRL_PIX_CLKGATE,
> -		&clkctrl_regs->hw_clkctrl_pix_set);
> -	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
> -			CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
> -			k_best << CLKCTRL_PIX_DIV_OFFSET);
> -
> -	while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
> -		;
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	writeb(CLKCTRL_FRAC_CLKGATE,
>  		&clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
>  	writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
> diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c
> index 381264b8a18d..d212d0fa529d 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c
> @@ -13,14 +13,11 @@
>  #include <asm/arch/iomux.h>
>  #include <asm/arch/imx-regs.h>
>  
> -#if	defined(CONFIG_MX23)
> -#define	DRIVE_OFFSET	0x200
> -#define	PULL_OFFSET	0x400
> -#elif	defined(CONFIG_MX28)
> +#if	defined(CONFIG_MX28)
>  #define	DRIVE_OFFSET	0x300
>  #define	PULL_OFFSET	0x600
>  #else
> -#error "Please select CONFIG_MX23 or CONFIG_MX28"
> +#error "Please select CONFIG_MX28"
>  #endif
>  
>  /*
> diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg
> deleted file mode 100644
> index ab2183ed3795..000000000000
> --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -DISPLAYPROGRESS
> -SECTION 0x0 BOOTABLE
> - TAG LAST
> - LOAD     0x1000     spl/u-boot-spl.bin
> - CALL     0x1000     0x0
> diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
> deleted file mode 100644
> index e7028092a2c3..000000000000
> --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -DISPLAYPROGRESS
> -SECTION 0x0 BOOTABLE
> - TAG LAST
> - LOAD     0x1000     spl/u-boot-spl.bin
> - CALL     0x1000     0x0
> - LOAD     0x40002000 u-boot.bin
> - CALL     0x40002000 0x0
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
> index 1501d7df0dc6..d44167e4e90c 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
> @@ -39,42 +39,13 @@ void early_delay(int delay)
>  		;
>  }
>  
> -#if defined(CONFIG_MX23)
> -#define	MUX_CONFIG_BOOTMODE_PAD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
> -static const iomux_cfg_t iomux_boot[] = {
> -	MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
> -	MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
> -	MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
> -	MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
> -	MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
> -	MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
> -};
> -#endif
> -
>  static uint8_t mxs_get_bootmode_index(void)
>  {
>  	uint8_t bootmode = 0;
>  	int i;
>  	uint8_t masked;
>  
> -#if defined(CONFIG_MX23)
> -	/* Setup IOMUX of bootmode pads to GPIO */
> -	mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
> -
> -	/* Setup bootmode pins as GPIO input */
> -	gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
> -	gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
> -	gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2);
> -	gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3);
> -	gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5);
> -
> -	/* Read bootmode pads */
> -	bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
> -	bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
> -	bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
> -	bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
> -	bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	/* The global boot mode will be detected by ROM code and its value
>  	 * is stored at the fixed address 0x00019BF0 in OCRAM.
>  	 */
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> index a94803ee93d9..c56b620f1ffa 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> @@ -71,21 +71,6 @@ __weak uint32_t mxs_dram_vals[] = {
>  	0x00040004, 0x00000000, 0x00000000, 0x00000000,
>  	0x00000000, 0xffffffff
>  
> -/*
> - * i.MX23 DDR at 133MHz
> - */
> -#elif defined(CONFIG_MX23)
> -	0x01010001, 0x00010100, 0x01000101, 0x00000001,
> -	0x00000101, 0x00000000, 0x00010000, 0x01000001,
> -	0x00000000, 0x00000001, 0x07000200, 0x00070202,
> -	0x02020000, 0x04040a01, 0x00000201, 0x02040000,
> -	0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
> -	0x02061521, 0x0000000a, 0x00080008, 0x00200020,
> -	0x00200020, 0x00200020, 0x000003f7, 0x00000000,
> -	0x00000000, 0x00000020, 0x00000020, 0x00c80000,
> -	0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
> -	0x00000101, 0x00040001, 0x00000000, 0x00000000,
> -	0x00010000
>  #else
>  #error Unsupported memory initialization
>  #endif
> @@ -144,10 +129,7 @@ static void mxs_mem_init_clock(void)
>  {
>  	struct mxs_clkctrl_regs *clkctrl_regs =
>  		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
> -#if defined(CONFIG_MX23)
> -	/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
> -	const unsigned char divider = 33;
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
>  	const unsigned char divider = 21;
>  #endif
> @@ -247,67 +229,6 @@ uint32_t mxs_mem_get_size(void)
>  	return sz;
>  }
>  
> -#ifdef CONFIG_MX23
> -static void mx23_mem_setup_vddmem(void)
> -{
> -	struct mxs_power_regs *power_regs =
> -		(struct mxs_power_regs *)MXS_POWER_BASE;
> -
> -	debug("SPL: Setting mx23 VDDMEM\n");
> -
> -	/* We must wait before and after disabling the current limiter! */
> -	early_delay(10000);
> -
> -	clrbits_le32(&power_regs->hw_power_vddmemctrl,
> -		POWER_VDDMEMCTRL_ENABLE_ILIMIT);
> -
> -	early_delay(10000);
> -
> -}
> -
> -static void mx23_mem_init(void)
> -{
> -	debug("SPL: Initialising mx23 SDRAM Controller\n");
> -
> -	/*
> -	 * Reset/ungate the EMI block. This is essential, otherwise the system
> -	 * suffers from memory instability. This thing is mx23 specific and is
> -	 * no longer present on mx28.
> -	 */
> -	mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
> -
> -	mx23_mem_setup_vddmem();
> -
> -	/*
> -	 * Configure the DRAM registers
> -	 */
> -
> -	/* Clear START and SREFRESH bit from DRAM_CTL8 */
> -	clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
> -
> -	initialize_dram_values();
> -
> -	/* Set START bit in DRAM_CTL8 */
> -	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
> -
> -	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
> -
> -	/* Wait for EMI_STAT bit DRAM_HALTED */
> -	for (;;) {
> -		if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
> -			break;
> -		early_delay(1000);
> -	}
> -
> -	/* Adjust EMI port priority. */
> -	clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
> -	early_delay(20000);
> -
> -	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
> -	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
> -}
> -#endif
> -
>  #ifdef CONFIG_MX28
>  static void mx28_mem_init(void)
>  {
> @@ -349,9 +270,7 @@ void mxs_mem_init(void)
>  
>  	mxs_mem_setup_vdda();
>  
> -#if defined(CONFIG_MX23)
> -	mx23_mem_init();
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	mx28_mem_init();
>  #endif
>  
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
> index 35ea71a5ba89..095ad9230fa8 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
> @@ -939,13 +939,6 @@ static void mxs_power_configure_power_source(void)
>  	mxs_init_batt_bo();
>  
>  	mxs_switch_vddd_to_dcdc_source();
> -
> -#ifdef CONFIG_MX23
> -	/* Fire up the VDDMEM LinReg now that we're all set. */
> -	debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
> -	writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
> -		&power_regs->hw_power_vddmemctrl);
> -#endif
>  }
>  
>  /**
> @@ -1065,9 +1058,7 @@ struct mxs_vddx_cfg {
>  static const struct mxs_vddx_cfg mxs_vddio_cfg = {
>  	.reg			= &(((struct mxs_power_regs *)MXS_POWER_BASE)->
>  					hw_power_vddioctrl),
> -#if defined(CONFIG_MX23)
> -	.step_mV		= 25,
> -#else
> +#if defined(CONFIG_MX28)
>  	.step_mV		= 50,
>  #endif
>  	.lowest_mV		= 2800,
> @@ -1092,21 +1083,6 @@ static const struct mxs_vddx_cfg mxs_vddd_cfg = {
>  	.bo_offset_offset	= POWER_VDDDCTRL_BO_OFFSET_OFFSET,
>  };
>  
> -#ifdef CONFIG_MX23
> -static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
> -	.reg			= &(((struct mxs_power_regs *)MXS_POWER_BASE)->
> -					hw_power_vddmemctrl),
> -	.step_mV		= 50,
> -	.lowest_mV		= 1700,
> -	.powered_by_linreg	= NULL,
> -	.trg_mask		= POWER_VDDMEMCTRL_TRG_MASK,
> -	.bo_irq			= 0,
> -	.bo_enirq		= 0,
> -	.bo_offset_mask		= 0,
> -	.bo_offset_offset	= 0,
> -};
> -#endif
> -
>  /**
>   * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
>   * @cfg:		Configuration data of the DC-DC converter rail
> @@ -1210,24 +1186,6 @@ static void mxs_setup_batt_detect(void)
>  	early_delay(10);
>  }
>  
> -/**
> - * mxs_ungate_power() - Ungate the POWER block
> - *
> - * This function ungates clock to the power block. In case the power block
> - * was still gated at this point, it will not be possible to configure the
> - * block and therefore the power initialization would fail. This function
> - * is only needed on i.MX233, on i.MX28 the power block is always ungated.
> - */
> -static void mxs_ungate_power(void)
> -{
> -#ifdef CONFIG_MX23
> -	struct mxs_power_regs *power_regs =
> -		(struct mxs_power_regs *)MXS_POWER_BASE;
> -
> -	writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
> -#endif
> -}
> -
>  /**
>   * mxs_power_init() - The power block init main function
>   *
> @@ -1241,8 +1199,6 @@ void mxs_power_init(void)
>  
>  	debug("SPL: Initialising Power Block\n");
>  
> -	mxs_ungate_power();
> -
>  	mxs_power_clock2xtal();
>  	mxs_power_set_auto_restart();
>  	mxs_power_set_linreg();
> @@ -1258,10 +1214,6 @@ void mxs_power_init(void)
>  
>  	debug("SPL: Setting VDDD to 1V55 (brownout @ 1v400)\n");
>  	mxs_power_set_vddx(&mxs_vddd_cfg, 1550, 1400);
> -#ifdef CONFIG_MX23
> -	debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
> -	mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
> -#endif
>  	writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
>  		POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
>  		POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
> diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c
> index 5ab4ed0c5a3d..a5dd9a838e87 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/timer.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
> @@ -18,9 +18,7 @@
>  #include <linux/delay.h>
>  
>  /* Maximum fixed count */
> -#if defined(CONFIG_MX23)
> -#define TIMER_LOAD_VAL 0xffff
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define TIMER_LOAD_VAL 0xffffffff
>  #endif
>  
> @@ -59,9 +57,7 @@ int timer_init(void)
>  	mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
>  
>  	/* Set fixed_count to 0 */
> -#if defined(CONFIG_MX23)
> -	writel(0, &timrot_regs->hw_timrot_timcount0);
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	writel(0, &timrot_regs->hw_timrot_fixed_count0);
>  #endif
>  
> @@ -71,9 +67,7 @@ int timer_init(void)
>  		&timrot_regs->hw_timrot_timctrl0);
>  
>  	/* Set fixed_count to maximal value */
> -#if defined(CONFIG_MX23)
> -	writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
>  #endif
>  
> diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
> deleted file mode 100644
> index 3a51879d5e4a..000000000000
> --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -options {
> -	driveTag = 0x00;
> -	flags = 0x01;
> -}
> -
> -sources {
> -	u_boot_spl="spl/u-boot-spl.bin";
> -	u_boot="u-boot.bin";
> -}
> -
> -section (0) {
> -	load u_boot_spl > 0x0000;
> -	load ivt (entry = 0x0014) > 0x8000;
> -	call 0x8000;
> -
> -	load u_boot > 0x40000100;
> -	call 0x40000100;
> -}
> diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
> index f853c484be7d..c099c65c9608 100644
> --- a/arch/arm/include/asm/arch-mxs/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
> @@ -25,11 +25,6 @@
>  #include <asm/arch/regs-usb.h>
>  #include <asm/arch/regs-usbphy.h>
>  
> -#ifdef CONFIG_MX23
> -#include <asm/arch/regs-clkctrl-mx23.h>
> -#include <asm/arch/regs-power-mx23.h>
> -#endif
> -
>  #ifdef CONFIG_MX28
>  #include <asm/arch/regs-clkctrl-mx28.h>
>  #include <asm/arch/regs-power-mx28.h>
> diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/arch/arm/include/asm/arch-mxs/iomux-mx23.h
> deleted file mode 100644
> index 2706efa750a2..000000000000
> --- a/arch/arm/include/asm/arch-mxs/iomux-mx23.h
> +++ /dev/null
> @@ -1,349 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria at canonical.com>
> - * Copyright (C) 2010 Freescale Semiconductor, Inc.
> - */
> -
> -#ifndef __MACH_IOMUX_MX23_H__
> -#define __MACH_IOMUX_MX23_H__
> -
> -#include <asm/arch/iomux.h>
> -
> -/*
> - * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
> - * See also iomux.h
> - *
> - *									BANK	PIN	MUX
> - */
> -/* MUXSEL_0 */
> -#define MX23_PAD_GPMI_D00__GPMI_D00		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D01__GPMI_D01		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D02__GPMI_D02		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D03__GPMI_D03		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D04__GPMI_D04		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D05__GPMI_D05		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D06__GPMI_D06		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D07__GPMI_D07		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D08__GPMI_D08		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D09__GPMI_D09		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D10__GPMI_D10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D11__GPMI_D11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D12__GPMI_D12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D13__GPMI_D13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D14__GPMI_D14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_D15__GPMI_D15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_CLE__GPMI_CLE		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_ALE__GPMI_ALE		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_WPN__GPMI_WPN		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_WRN__GPMI_WRN		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_RDN__GPMI_RDN		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
> -#define MX23_PAD_AUART1_CTS__AUART1_CTS		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
> -#define MX23_PAD_AUART1_RTS__AUART1_RTS		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
> -#define MX23_PAD_AUART1_RX__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
> -#define MX23_PAD_AUART1_TX__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
> -#define MX23_PAD_I2C_SCL__I2C_SCL		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
> -#define MX23_PAD_I2C_SDA__I2C_SDA		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
> -
> -#define MX23_PAD_LCD_D00__LCD_D00		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D01__LCD_D01		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D02__LCD_D02		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D03__LCD_D03		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D04__LCD_D04		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D05__LCD_D05		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D06__LCD_D06		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D07__LCD_D07		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D08__LCD_D08		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D09__LCD_D09		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D10__LCD_D10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D11__LCD_D11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D12__LCD_D12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D13__LCD_D13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D14__LCD_D14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D15__LCD_D15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D16__LCD_D16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_D17__LCD_D17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_RESET__LCD_RESET		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_RS__LCD_RS			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_WR__LCD_WR			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_CS__LCD_CS			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
> -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
> -#define MX23_PAD_PWM0__PWM0			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
> -#define MX23_PAD_PWM1__PWM1			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
> -#define MX23_PAD_PWM2__PWM2			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
> -#define MX23_PAD_PWM3__PWM3			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
> -#define MX23_PAD_PWM4__PWM4			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
> -
> -#define MX23_PAD_SSP1_CMD__SSP1_CMD		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
> -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
> -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
> -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
> -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
> -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
> -#define MX23_PAD_SSP1_SCK__SSP1_SCK		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
> -#define MX23_PAD_ROTARYA__ROTARYA		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
> -#define MX23_PAD_ROTARYB__ROTARYB		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A00__EMI_A00		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A01__EMI_A01		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A02__EMI_A02		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A03__EMI_A03		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A04__EMI_A04		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A05__EMI_A05		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A06__EMI_A06		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A07__EMI_A07		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A08__EMI_A08		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A09__EMI_A09		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A10__EMI_A10		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A11__EMI_A11		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_A12__EMI_A12		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_BA0__EMI_BA0		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_BA1__EMI_BA1		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_CASN__EMI_CASN		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_CE0N__EMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_CE1N__EMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
> -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_CKE__EMI_CKE		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_RASN__EMI_RASN		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_WEN__EMI_WEN		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
> -
> -#define MX23_PAD_EMI_D00__EMI_D00		MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D01__EMI_D01		MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D02__EMI_D02		MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D03__EMI_D03		MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D04__EMI_D04		MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D05__EMI_D05		MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D06__EMI_D06		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D07__EMI_D07		MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D08__EMI_D08		MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D09__EMI_D09		MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D10__EMI_D10		MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D11__EMI_D11		MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D12__EMI_D12		MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D13__EMI_D13		MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D14__EMI_D14		MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_D15__EMI_D15		MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_DQM0__EMI_DQM0		MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_DQM1__EMI_DQM1		MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_DQS0__EMI_DQS0		MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_DQS1__EMI_DQS1		MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_CLK__EMI_CLK		MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
> -#define MX23_PAD_EMI_CLKN__EMI_CLKN		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
> -
> -/* MUXSEL_1 */
> -#define MX23_PAD_GPMI_D00__LCD_D8		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D01__LCD_D9		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D02__LCD_D10		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D03__LCD_D11		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D04__LCD_D12		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D05__LCD_D13		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D06__LCD_D14		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D07__LCD_D15		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D08__LCD_D18		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D09__LCD_D19		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D10__LCD_D20		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D11__LCD_D21		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D12__LCD_D22		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D13__LCD_D23		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D14__AUART2_RX		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_D15__AUART2_TX		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_CLE__LCD_D16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_ALE__LCD_D17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
> -#define MX23_PAD_GPMI_CE2N__ATA_A2		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
> -#define MX23_PAD_AUART1_RTS__IR_CLK		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
> -#define MX23_PAD_AUART1_RX__IR_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
> -#define MX23_PAD_AUART1_TX__IR_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
> -#define MX23_PAD_I2C_SCL__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
> -#define MX23_PAD_I2C_SDA__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
> -
> -#define MX23_PAD_LCD_D00__ETM_DA8		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D01__ETM_DA9		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D02__ETM_DA10		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D03__ETM_DA11		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D04__ETM_DA12		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D05__ETM_DA13		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D06__ETM_DA14		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D07__ETM_DA15		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D08__ETM_DA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D09__ETM_DA1		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D10__ETM_DA2		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D11__ETM_DA3		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D12__ETM_DA4		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D13__ETM_DA5		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D14__ETM_DA6		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_D15__ETM_DA7		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_RESET__ETM_TCTL		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_RS__ETM_TCLK		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_ENABLE__I2C_SCL		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_HSYNC__I2C_SDA		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
> -#define MX23_PAD_LCD_VSYNC__LCD_BUSY		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
> -#define MX23_PAD_PWM0__ROTARYA			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
> -#define MX23_PAD_PWM1__ROTARYB			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
> -#define MX23_PAD_PWM2__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
> -#define MX23_PAD_PWM3__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
> -#define MX23_PAD_PWM4__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
> -
> -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
> -#define MX23_PAD_SSP1_DATA1__I2C_SCL		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
> -#define MX23_PAD_SSP1_DATA2__I2C_SDA		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
> -#define MX23_PAD_ROTARYA__AUART2_RTS		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
> -#define MX23_PAD_ROTARYB__AUART2_CTS		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
> -
> -/* MUXSEL_2 */
> -#define MX23_PAD_GPMI_D00__SSP2_DATA0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D01__SSP2_DATA1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D02__SSP2_DATA2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D03__SSP2_DATA3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D04__SSP2_DATA4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D05__SSP2_DATA5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D06__SSP2_DATA6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D07__SSP2_DATA7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D08__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D09__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D10__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D11__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_D15__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_RDY1__SSP2_CMD		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
> -#define MX23_PAD_GPMI_WRN__SSP2_SCK		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
> -#define MX23_PAD_AUART1_CTS__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
> -#define MX23_PAD_AUART1_RTS__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
> -#define MX23_PAD_AUART1_RX__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
> -#define MX23_PAD_AUART1_TX__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
> -#define MX23_PAD_I2C_SCL__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
> -#define MX23_PAD_I2C_SDA__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
> -
> -#define MX23_PAD_LCD_D08__SAIF2_SDATA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
> -#define MX23_PAD_LCD_D09__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
> -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK	MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
> -#define MX23_PAD_LCD_D11__SAIF_LRCLK		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
> -#define MX23_PAD_LCD_D12__SAIF2_SDATA1		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
> -#define MX23_PAD_LCD_D13__SAIF2_SDATA2		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
> -#define MX23_PAD_LCD_D14__SAIF1_SDATA2		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
> -#define MX23_PAD_LCD_D15__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
> -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK	MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
> -#define MX23_PAD_LCD_RESET__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
> -#define MX23_PAD_PWM0__DUART_RX			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
> -#define MX23_PAD_PWM1__DUART_TX			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
> -#define MX23_PAD_PWM3__AUART1_CTS		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
> -#define MX23_PAD_PWM4__AUART1_RTS		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
> -
> -#define MX23_PAD_SSP1_CMD__JTAG_TDO		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
> -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
> -#define MX23_PAD_SSP1_DATA0__JTAG_TDI		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
> -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
> -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
> -#define MX23_PAD_SSP1_DATA3__JTAG_TMS		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
> -#define MX23_PAD_SSP1_SCK__JTAG_TRST		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
> -#define MX23_PAD_ROTARYA__SPDIF			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
> -#define MX23_PAD_ROTARYB__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
> -
> -/* MUXSEL_GPIO */
> -#define MX23_PAD_GPMI_D00__GPIO_0_0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D01__GPIO_0_1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D02__GPIO_0_2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D03__GPIO_0_3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D04__GPIO_0_4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D05__GPIO_0_5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D06__GPIO_0_6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D07__GPIO_0_7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D08__GPIO_0_8		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D09__GPIO_0_9		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D10__GPIO_0_10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D11__GPIO_0_11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D12__GPIO_0_12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D13__GPIO_0_13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D14__GPIO_0_14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_D15__GPIO_0_15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_CLE__GPIO_0_16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_ALE__GPIO_0_17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_CE2N__GPIO_0_18		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_RDY0__GPIO_0_19		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_RDY1__GPIO_0_20		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_RDY2__GPIO_0_21		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_RDY3__GPIO_0_22		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_WPN__GPIO_0_23		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_WRN__GPIO_0_24		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_RDN__GPIO_0_25		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_AUART1_CTS__GPIO_0_26		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_AUART1_RTS__GPIO_0_27		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_AUART1_RX__GPIO_0_28		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_AUART1_TX__GPIO_0_29		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_I2C_SCL__GPIO_0_30		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_I2C_SDA__GPIO_0_31		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
> -
> -#define MX23_PAD_LCD_D00__GPIO_1_0		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D01__GPIO_1_1		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D02__GPIO_1_2		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D03__GPIO_1_3		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D04__GPIO_1_4		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D05__GPIO_1_5		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D06__GPIO_1_6		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D07__GPIO_1_7		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D08__GPIO_1_8		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D09__GPIO_1_9		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D10__GPIO_1_10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D11__GPIO_1_11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D12__GPIO_1_12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D13__GPIO_1_13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D14__GPIO_1_14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D15__GPIO_1_15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D16__GPIO_1_16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_D17__GPIO_1_17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_RESET__GPIO_1_18		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_RS__GPIO_1_19		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_WR__GPIO_1_20		MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_CS__GPIO_1_21		MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_DOTCK__GPIO_1_22		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_ENABLE__GPIO_1_23		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_HSYNC__GPIO_1_24		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_LCD_VSYNC__GPIO_1_25		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_PWM0__GPIO_1_26		MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_PWM1__GPIO_1_27		MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_PWM2__GPIO_1_28		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_PWM3__GPIO_1_29		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_PWM4__GPIO_1_30		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
> -
> -#define MX23_PAD_SSP1_CMD__GPIO_2_0		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_SSP1_DETECT__GPIO_2_1		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_SSP1_DATA0__GPIO_2_2		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_SSP1_DATA1__GPIO_2_3		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_SSP1_DATA2__GPIO_2_4		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_SSP1_DATA3__GPIO_2_5		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_SSP1_SCK__GPIO_2_6		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_ROTARYA__GPIO_2_7		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_ROTARYB__GPIO_2_8		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A00__GPIO_2_9		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A01__GPIO_2_10		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A02__GPIO_2_11		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A03__GPIO_2_12		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A04__GPIO_2_13		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A05__GPIO_2_14		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A06__GPIO_2_15		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A07__GPIO_2_16		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A08__GPIO_2_17		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A09__GPIO_2_18		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A10__GPIO_2_19		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A11__GPIO_2_20		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_A12__GPIO_2_21		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_BA0__GPIO_2_22		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_BA1__GPIO_2_23		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_CASN__GPIO_2_24		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_CE0N__GPIO_2_25		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_CE1N__GPIO_2_26		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_CE1N__GPIO_2_27		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_GPMI_CE0N__GPIO_2_28		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_CKE__GPIO_2_29		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_RASN__GPIO_2_30		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
> -#define MX23_PAD_EMI_WEN__GPIO_2_31		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
> -
> -#endif /* __MACH_IOMUX_MX23_H__ */
> diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h
> index 44d40cade879..c016d1b25534 100644
> --- a/arch/arm/include/asm/arch-mxs/regs-base.h
> +++ b/arch/arm/include/asm/arch-mxs/regs-base.h
> @@ -14,52 +14,10 @@
>  #ifndef __MXS_REGS_BASE_H__
>  #define __MXS_REGS_BASE_H__
>  
> -/*
> - * Register base addresses for i.MX23
> - */
> -#if defined(CONFIG_MX23)
> -#define	MXS_ICOLL_BASE		0x80000000
> -#define	MXS_APBH_BASE		0x80004000
> -#define	MXS_ECC8_BASE		0x80008000
> -#define	MXS_BCH_BASE		0x8000A000
> -#define	MXS_GPMI_BASE		0x8000C000
> -#define	MXS_SSP0_BASE		0x80010000
> -#define	MXS_SSP1_BASE		0x80034000
> -#define	MXS_ETM_BASE		0x80014000
> -#define	MXS_PINCTRL_BASE	0x80018000
> -#define	MXS_DIGCTL_BASE		0x8001C000
> -#define	MXS_EMI_BASE		0x80020000
> -#define	MXS_APBX_BASE		0x80024000
> -#define	MXS_DCP_BASE		0x80028000
> -#define	MXS_PXP_BASE		0x8002A000
> -#define	MXS_OCOTP_BASE		0x8002C000
> -#define	MXS_AXI_BASE		0x8002E000
> -#define	MXS_LCDIF_BASE		0x80030000
> -#define	MXS_SSP1_BASE		0x80034000
> -#define	MXS_TVENC_BASE		0x80038000
> -#define	MXS_CLKCTRL_BASE	0x80040000
> -#define	MXS_SAIF0_BASE		0x80042000
> -#define	MXS_POWER_BASE		0x80044000
> -#define	MXS_SAIF1_BASE		0x80046000
> -#define	MXS_AUDIOOUT_BASE	0x80048000
> -#define	MXS_AUDIOIN_BASE	0x8004C000
> -#define	MXS_LRADC_BASE		0x80050000
> -#define	MXS_SPDIF_BASE		0x80054000
> -#define	MXS_I2C0_BASE		0x80058000
> -#define	MXS_RTC_BASE		0x8005C000
> -#define	MXS_PWM_BASE		0x80064000
> -#define	MXS_TIMROT_BASE		0x80068000
> -#define	MXS_UARTAPP0_BASE	0x8006C000
> -#define	MXS_UARTAPP1_BASE	0x8006E000
> -#define	MXS_UARTDBG_BASE	0x80070000
> -#define	MXS_USBPHY0_BASE	0x8007C000
> -#define	MXS_USBCTRL0_BASE	0x80080000
> -#define	MXS_DRAM_BASE		0x800E0000
> -
>  /*
>   * Register base addresses for i.MX28
>   */
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	MXS_ICOL_BASE		0x80000000
>  #define	MXS_HSADC_BASE		0x80002000
>  #define	MXS_APBH_BASE		0x80004000
> @@ -114,7 +72,7 @@
>  #define	MXS_ENET0_BASE		0x800F0000
>  #define	MXS_ENET1_BASE		0x800F4000
>  #else
> -#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28
> +#error Unkown SoC. Please set CONFIG_MX28
>  #endif
>  
>  #endif /* __MXS_REGS_BASE_H__ */
> diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
> deleted file mode 100644
> index 50fdc9cd0326..000000000000
> --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
> +++ /dev/null
> @@ -1,209 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Freescale i.MX23 CLKCTRL Register Definitions
> - *
> - * Copyright (C) 2012 Marek Vasut <marek.vasut at gmail.com>
> - * on behalf of DENX Software Engineering GmbH
> - *
> - * Based on code from LTIB:
> - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
> - */
> -
> -#ifndef __MX23_REGS_CLKCTRL_H__
> -#define __MX23_REGS_CLKCTRL_H__
> -
> -#include <asm/mach-imx/regs-common.h>
> -
> -#ifndef	__ASSEMBLY__
> -struct mxs_clkctrl_regs {
> -	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
> -	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
> -	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
> -	mxs_reg_32(hw_clkctrl_cpu)		/* 0x20 */
> -	mxs_reg_32(hw_clkctrl_hbus)		/* 0x30 */
> -	mxs_reg_32(hw_clkctrl_xbus)		/* 0x40 */
> -	mxs_reg_32(hw_clkctrl_xtal)		/* 0x50 */
> -	mxs_reg_32(hw_clkctrl_pix)		/* 0x60 */
> -	uint32_t	hw_clkctrl_ssp0;	/* 0x70 */
> -	uint32_t	reserved_ssp0[3];	/* 0x74-0x7c */
> -	uint32_t	hw_clkctrl_gpmi;	/* 0x80 */
> -	uint32_t	reserved_gpmi[3];	/* 0x84-0x8c */
> -	mxs_reg_32(hw_clkctrl_spdif)		/* 0x90 */
> -	mxs_reg_32(hw_clkctrl_emi)		/* 0xa0 */
> -
> -	uint32_t	reserved1[4];
> -
> -	mxs_reg_32(hw_clkctrl_saif0)		/* 0xc0 */
> -	mxs_reg_32(hw_clkctrl_tv)		/* 0xd0 */
> -	mxs_reg_32(hw_clkctrl_etm)		/* 0xe0 */
> -	mxs_reg_8(hw_clkctrl_frac0)		/* 0xf0 */
> -	mxs_reg_8(hw_clkctrl_frac1)		/* 0x100 */
> -	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x110 */
> -	mxs_reg_32(hw_clkctrl_reset)		/* 0x120 */
> -	mxs_reg_32(hw_clkctrl_status)		/* 0x130 */
> -	mxs_reg_32(hw_clkctrl_version)		/* 0x140 */
> -};
> -#endif
> -
> -#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
> -#define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
> -#define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
> -#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
> -#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
> -#define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
> -#define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
> -#define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
> -#define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
> -#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
> -#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
> -#define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
> -#define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
> -#define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
> -#define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
> -#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
> -#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
> -#define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
> -#define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
> -#define	CLKCTRL_PLL0CTRL0_POWER			(1 << 16)
> -
> -#define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
> -#define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
> -#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
> -#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
> -
> -#define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
> -#define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
> -#define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
> -#define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
> -#define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
> -#define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
> -#define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
> -#define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
> -#define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
> -
> -#define	CLKCTRL_HBUS_BUSY			(1 << 29)
> -#define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 28)
> -#define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 27)
> -#define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
> -#define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
> -#define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
> -#define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
> -#define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
> -#define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
> -#define	CLKCTRL_HBUS_AUTO_SLOW_MODE		(1 << 20)
> -#define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
> -#define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
> -#define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
> -#define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
> -#define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
> -#define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
> -#define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
> -#define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
> -#define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
> -#define	CLKCTRL_HBUS_DIV_MASK			0x1f
> -#define	CLKCTRL_HBUS_DIV_OFFSET			0
> -
> -#define	CLKCTRL_XBUS_BUSY			(1 << 31)
> -#define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
> -#define	CLKCTRL_XBUS_DIV_MASK			0x3ff
> -#define	CLKCTRL_XBUS_DIV_OFFSET			0
> -
> -#define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
> -#define	CLKCTRL_XTAL_FILT_CLK24M_GATE		(1 << 30)
> -#define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
> -#define	CLKCTRL_XTAL_DRI_CLK24M_GATE		(1 << 28)
> -#define	CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE		(1 << 27)
> -#define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
> -#define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
> -#define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
> -
> -#define	CLKCTRL_PIX_CLKGATE			(1 << 31)
> -#define	CLKCTRL_PIX_BUSY			(1 << 29)
> -#define	CLKCTRL_PIX_DIV_FRAC_EN			(1 << 12)
> -#define	CLKCTRL_PIX_DIV_MASK			0xfff
> -#define	CLKCTRL_PIX_DIV_OFFSET			0
> -
> -#define	CLKCTRL_SSP_CLKGATE			(1 << 31)
> -#define	CLKCTRL_SSP_BUSY			(1 << 29)
> -#define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
> -#define	CLKCTRL_SSP_DIV_MASK			0x1ff
> -#define	CLKCTRL_SSP_DIV_OFFSET			0
> -
> -#define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
> -#define	CLKCTRL_GPMI_BUSY			(1 << 29)
> -#define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
> -#define	CLKCTRL_GPMI_DIV_MASK			0x3ff
> -#define	CLKCTRL_GPMI_DIV_OFFSET			0
> -
> -#define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
> -
> -#define	CLKCTRL_EMI_CLKGATE			(1 << 31)
> -#define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
> -#define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
> -#define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
> -#define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
> -#define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
> -#define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
> -#define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
> -#define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
> -#define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
> -#define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
> -#define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
> -
> -#define	CLKCTRL_IR_CLKGATE			(1 << 31)
> -#define	CLKCTRL_IR_AUTO_DIV			(1 << 29)
> -#define	CLKCTRL_IR_IR_BUSY			(1 << 28)
> -#define	CLKCTRL_IR_IROV_BUSY			(1 << 27)
> -#define	CLKCTRL_IR_IROV_DIV_MASK		(0x1ff << 16)
> -#define	CLKCTRL_IR_IROV_DIV_OFFSET		16
> -#define	CLKCTRL_IR_IR_DIV_MASK			0x3ff
> -#define	CLKCTRL_IR_IR_DIV_OFFSET		0
> -
> -#define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
> -#define	CLKCTRL_SAIF0_BUSY			(1 << 29)
> -#define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
> -#define	CLKCTRL_SAIF0_DIV_MASK			0xffff
> -#define	CLKCTRL_SAIF0_DIV_OFFSET		0
> -
> -#define	CLKCTRL_TV_CLK_TV108M_GATE		(1 << 31)
> -#define	CLKCTRL_TV_CLK_TV_GATE			(1 << 30)
> -
> -#define	CLKCTRL_ETM_CLKGATE			(1 << 31)
> -#define	CLKCTRL_ETM_BUSY			(1 << 29)
> -#define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 6)
> -#define	CLKCTRL_ETM_DIV_MASK			0x3f
> -#define	CLKCTRL_ETM_DIV_OFFSET			0
> -
> -#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
> -#define	CLKCTRL_FRAC_STABLE			(1 << 6)
> -#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
> -#define	CLKCTRL_FRAC_FRAC_OFFSET		0
> -#define	CLKCTRL_FRAC0_CPU			0
> -#define	CLKCTRL_FRAC0_EMI			1
> -#define	CLKCTRL_FRAC0_PIX			2
> -#define	CLKCTRL_FRAC0_IO0			3
> -#define	CLKCTRL_FRAC1_VID			3
> -
> -#define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
> -#define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 7)
> -#define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 6)
> -#define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 5)
> -#define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 4)
> -#define	CLKCTRL_CLKSEQ_BYPASS_IR		(1 << 3)
> -#define	CLKCTRL_CLKSEQ_BYPASS_PIX		(1 << 1)
> -#define	CLKCTRL_CLKSEQ_BYPASS_SAIF		(1 << 0)
> -
> -#define	CLKCTRL_RESET_CHIP			(1 << 1)
> -#define	CLKCTRL_RESET_DIG			(1 << 0)
> -
> -#define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
> -#define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
> -
> -#define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
> -#define	CLKCTRL_VERSION_MAJOR_OFFSET		24
> -#define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
> -#define	CLKCTRL_VERSION_MINOR_OFFSET		16
> -#define	CLKCTRL_VERSION_STEP_MASK		0xffff
> -#define	CLKCTRL_VERSION_STEP_OFFSET		0
> -
> -#endif /* __MX23_REGS_CLKCTRL_H__ */
> diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
> deleted file mode 100644
> index a0dc78102301..000000000000
> --- a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
> +++ /dev/null
> @@ -1,344 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Freescale i.MX23 Power Controller Register Definitions
> - *
> - * Copyright (C) 2012 Marek Vasut <marex at denx.de>
> - */
> -
> -#ifndef __MX23_REGS_POWER_H__
> -#define __MX23_REGS_POWER_H__
> -
> -#include <asm/mach-imx/regs-common.h>
> -
> -#ifndef	__ASSEMBLY__
> -struct mxs_power_regs {
> -	mxs_reg_32(hw_power_ctrl)
> -	mxs_reg_32(hw_power_5vctrl)
> -	mxs_reg_32(hw_power_minpwr)
> -	mxs_reg_32(hw_power_charge)
> -	uint32_t	hw_power_vdddctrl;
> -	uint32_t	reserved_vddd[3];
> -	uint32_t	hw_power_vddactrl;
> -	uint32_t	reserved_vdda[3];
> -	uint32_t	hw_power_vddioctrl;
> -	uint32_t	reserved_vddio[3];
> -	uint32_t	hw_power_vddmemctrl;
> -	uint32_t	reserved_vddmem[3];
> -	uint32_t	hw_power_dcdc4p2;
> -	uint32_t	reserved_dcdc4p2[3];
> -	uint32_t	hw_power_misc;
> -	uint32_t	reserved_misc[3];
> -	uint32_t	hw_power_dclimits;
> -	uint32_t	reserved_dclimits[3];
> -	mxs_reg_32(hw_power_loopctrl)
> -	uint32_t	hw_power_sts;
> -	uint32_t	reserved_sts[3];
> -	mxs_reg_32(hw_power_speed)
> -	uint32_t	hw_power_battmonitor;
> -	uint32_t	reserved_battmonitor[3];
> -
> -	uint32_t	reserved1[4];
> -
> -	mxs_reg_32(hw_power_reset)
> -
> -	uint32_t	reserved2[4];
> -
> -	mxs_reg_32(hw_power_special)
> -	mxs_reg_32(hw_power_version)
> -};
> -#endif
> -
> -#define	POWER_CTRL_CLKGATE				(1 << 30)
> -#define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
> -#define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
> -#define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
> -#define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
> -#define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
> -#define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
> -#define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
> -#define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
> -#define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
> -#define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
> -#define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
> -#define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
> -#define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
> -#define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
> -#define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
> -#define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
> -#define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
> -#define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
> -#define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
> -#define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
> -#define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
> -#define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
> -#define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
> -#define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
> -#define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
> -#define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
> -
> -#define	POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 28)
> -#define	POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		28
> -#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V3			(0x0 << 28)
> -#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V4			(0x1 << 28)
> -#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V5			(0x2 << 28)
> -#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V7			(0x3 << 28)
> -#define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
> -#define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
> -#define	POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x1 << 20)
> -#define	POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET		20
> -#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
> -#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
> -#define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
> -#define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
> -#define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
> -#define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
> -#define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
> -#define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
> -#define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
> -#define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
> -#define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
> -
> -#define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
> -#define	POWER_MINPWR_VDAC_DUMP_CTRL			(1 << 13)
> -#define	POWER_MINPWR_PWD_BO				(1 << 12)
> -#define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
> -#define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
> -#define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
> -#define	POWER_MINPWR_SELECT_OSC				(1 << 8)
> -#define	POWER_MINPWR_VBG_OFF				(1 << 7)
> -#define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
> -#define	POWER_MINPWR_HALFFETS				(1 << 5)
> -#define	POWER_MINPWR_LESSANA_I				(1 << 4)
> -#define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
> -#define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
> -#define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
> -#define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
> -
> -#define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
> -#define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
> -#define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
> -#define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
> -#define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
> -#define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
> -#define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
> -#define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
> -#define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
> -#define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
> -#define	POWER_CHARGE_ENABLE_CHARGER_RESISTORS		(1 << 21)
> -#define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
> -#define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
> -#define	POWER_CHARGE_USE_EXTERN_R			(1 << 17)
> -#define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
> -#define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
> -#define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
> -#define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
> -#define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
> -#define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
> -#define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
> -#define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
> -#define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
> -#define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
> -#define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
> -#define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
> -#define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
> -#define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
> -#define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
> -
> -#define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
> -#define	POWER_VDDDCTRL_ADJTN_OFFSET			28
> -#define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
> -#define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
> -#define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
> -#define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
> -#define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
> -#define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
> -#define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
> -#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
> -#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
> -#define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
> -#define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
> -#define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
> -#define	POWER_VDDDCTRL_TRG_MASK				0x1f
> -#define	POWER_VDDDCTRL_TRG_OFFSET			0
> -
> -#define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
> -#define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
> -#define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
> -#define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
> -#define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
> -#define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
> -#define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
> -#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
> -#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
> -#define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
> -#define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
> -#define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
> -#define	POWER_VDDACTRL_TRG_MASK				0x1f
> -#define	POWER_VDDACTRL_TRG_OFFSET			0
> -
> -#define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
> -#define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
> -#define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
> -#define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
> -#define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
> -#define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
> -#define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
> -#define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
> -#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
> -#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
> -#define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
> -#define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
> -#define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
> -#define	POWER_VDDIOCTRL_TRG_MASK			0x1f
> -#define	POWER_VDDIOCTRL_TRG_OFFSET			0
> -
> -#define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
> -#define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
> -#define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
> -#define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
> -#define	POWER_VDDMEMCTRL_TRG_OFFSET			0
> -
> -#define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
> -#define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
> -#define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
> -#define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
> -#define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
> -#define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
> -#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
> -#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
> -#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
> -#define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
> -#define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
> -#define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
> -#define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
> -#define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
> -#define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
> -#define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
> -#define	POWER_DCDC4P2_TRG_OFFSET			16
> -#define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
> -#define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
> -#define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
> -#define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
> -#define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
> -#define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
> -#define	POWER_DCDC4P2_BO_OFFSET				8
> -#define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
> -#define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
> -
> -#define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
> -#define	POWER_MISC_FREQSEL_OFFSET			4
> -#define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
> -#define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
> -#define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
> -#define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
> -#define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
> -#define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
> -#define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
> -#define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
> -#define	POWER_MISC_DELAY_TIMING				(1 << 2)
> -#define	POWER_MISC_TEST					(1 << 1)
> -#define	POWER_MISC_SEL_PLLCLK				(1 << 0)
> -
> -#define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
> -#define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
> -#define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
> -#define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
> -
> -#define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
> -#define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
> -#define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
> -#define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
> -#define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
> -#define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
> -#define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
> -#define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
> -#define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
> -#define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
> -#define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
> -#define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
> -#define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
> -#define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
> -#define	POWER_LOOPCTRL_DC_FF_OFFSET			8
> -#define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
> -#define	POWER_LOOPCTRL_DC_R_OFFSET			4
> -#define	POWER_LOOPCTRL_DC_C_MASK			0x3
> -#define	POWER_LOOPCTRL_DC_C_OFFSET			0
> -#define	POWER_LOOPCTRL_DC_C_MAX				0x0
> -#define	POWER_LOOPCTRL_DC_C_2X				0x1
> -#define	POWER_LOOPCTRL_DC_C_4X				0x2
> -#define	POWER_LOOPCTRL_DC_C_MIN				0x3
> -
> -#define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
> -#define	POWER_STS_PWRUP_SOURCE_OFFSET			24
> -#define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
> -#define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
> -#define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
> -#define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
> -#define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
> -#define	POWER_STS_PSWITCH_OFFSET			20
> -#define	POWER_STS_AVALID0_STATUS			(1 << 17)
> -#define	POWER_STS_BVALID0_STATUS			(1 << 16)
> -#define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
> -#define	POWER_STS_SESSEND0_STATUS			(1 << 14)
> -#define	POWER_STS_BATT_BO				(1 << 13)
> -#define	POWER_STS_VDD5V_FAULT				(1 << 12)
> -#define	POWER_STS_CHRGSTS				(1 << 11)
> -#define	POWER_STS_DCDC_4P2_BO				(1 << 10)
> -#define	POWER_STS_DC_OK					(1 << 9)
> -#define	POWER_STS_VDDIO_BO				(1 << 8)
> -#define	POWER_STS_VDDA_BO				(1 << 7)
> -#define	POWER_STS_VDDD_BO				(1 << 6)
> -#define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
> -#define	POWER_STS_VDD5V_DROOP				(1 << 4)
> -#define	POWER_STS_AVALID0				(1 << 3)
> -#define	POWER_STS_BVALID0				(1 << 2)
> -#define	POWER_STS_VBUSVALID0				(1 << 1)
> -#define	POWER_STS_SESSEND0				(1 << 0)
> -
> -#define	POWER_SPEED_STATUS_MASK				(0xff << 16)
> -#define	POWER_SPEED_STATUS_OFFSET			16
> -#define	POWER_SPEED_CTRL_MASK				0x3
> -#define	POWER_SPEED_CTRL_OFFSET				0
> -#define	POWER_SPEED_CTRL_SS_OFF				0x0
> -#define	POWER_SPEED_CTRL_SS_ON				0x1
> -#define	POWER_SPEED_CTRL_SS_ENABLE			0x3
> -
> -#define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
> -#define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
> -#define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
> -#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
> -#define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
> -#define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
> -#define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
> -
> -#define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
> -#define	POWER_RESET_UNLOCK_OFFSET			16
> -#define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
> -#define	POWER_RESET_PWD_OFF				(1 << 1)
> -#define	POWER_RESET_PWD					(1 << 0)
> -
> -#define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
> -#define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
> -#define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
> -#define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
> -
> -#define	POWER_SPECIAL_TEST_MASK				0xffffffff
> -#define	POWER_SPECIAL_TEST_OFFSET			0
> -
> -#define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
> -#define	POWER_VERSION_MAJOR_OFFSET			24
> -#define	POWER_VERSION_MINOR_MASK			(0xff << 16)
> -#define	POWER_VERSION_MINOR_OFFSET			16
> -#define	POWER_VERSION_STEP_MASK				0xffff
> -#define	POWER_VERSION_STEP_OFFSET			0
> -
> -#endif	/* __MX23_REGS_POWER_H__ */
> diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h
> index eeb7e7f44c06..26e620f93802 100644
> --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h
> +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h
> @@ -14,28 +14,7 @@
>  #include <asm/mach-imx/regs-common.h>
>  
>  #ifndef	__ASSEMBLY__
> -#if defined(CONFIG_MX23)
> -struct mxs_ssp_regs {
> -	mxs_reg_32(hw_ssp_ctrl0)
> -	mxs_reg_32(hw_ssp_cmd0)
> -	mxs_reg_32(hw_ssp_cmd1)
> -	mxs_reg_32(hw_ssp_compref)
> -	mxs_reg_32(hw_ssp_compmask)
> -	mxs_reg_32(hw_ssp_timing)
> -	mxs_reg_32(hw_ssp_ctrl1)
> -	mxs_reg_32(hw_ssp_data)
> -	mxs_reg_32(hw_ssp_sdresp0)
> -	mxs_reg_32(hw_ssp_sdresp1)
> -	mxs_reg_32(hw_ssp_sdresp2)
> -	mxs_reg_32(hw_ssp_sdresp3)
> -	mxs_reg_32(hw_ssp_status)
> -
> -	uint32_t	reserved1[12];
> -
> -	mxs_reg_32(hw_ssp_debug)
> -	mxs_reg_32(hw_ssp_version)
> -};
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  struct mxs_ssp_regs {
>  	mxs_reg_32(hw_ssp_ctrl0)
>  	mxs_reg_32(hw_ssp_cmd0)
> @@ -62,9 +41,7 @@ struct mxs_ssp_regs {
>  
>  static inline int mxs_ssp_bus_id_valid(int bus)
>  {
> -#if defined(CONFIG_MX23)
> -	const unsigned int mxs_ssp_chan_count = 2;
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	const unsigned int mxs_ssp_chan_count = 4;
>  #endif
>  
> @@ -79,9 +56,7 @@ static inline int mxs_ssp_bus_id_valid(int bus)
>  
>  static inline int mxs_ssp_clock_by_bus(unsigned int clock)
>  {
> -#if defined(CONFIG_MX23)
> -	return 0;
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	return clock;
>  #endif
>  }
> @@ -125,11 +100,6 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
>  #define	SSP_CTRL0_GET_RESP			(1 << 17)
>  #define	SSP_CTRL0_ENABLE			(1 << 16)
>  
> -#ifdef CONFIG_MX23
> -#define	SSP_CTRL0_XFER_COUNT_OFFSET		0
> -#define	SSP_CTRL0_XFER_COUNT_MASK		0xffff
> -#endif
> -
>  #define	SSP_CMD0_SOFT_TERMINATE			(1 << 26)
>  #define	SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
>  #define	SSP_CMD0_PRIM_BOOT_OP_EN		(1 << 24)
> @@ -137,12 +107,6 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
>  #define	SSP_CMD0_SLOW_CLKING_EN			(1 << 22)
>  #define	SSP_CMD0_CONT_CLKING_EN			(1 << 21)
>  #define	SSP_CMD0_APPEND_8CYC			(1 << 20)
> -#if defined(CONFIG_MX23)
> -#define	SSP_CMD0_BLOCK_SIZE_MASK		(0xf << 16)
> -#define	SSP_CMD0_BLOCK_SIZE_OFFSET		16
> -#define	SSP_CMD0_BLOCK_COUNT_MASK		(0xff << 8)
> -#define	SSP_CMD0_BLOCK_COUNT_OFFSET		8
> -#endif
>  #define	SSP_CMD0_CMD_MASK			0xff
>  #define	SSP_CMD0_CMD_OFFSET			0
>  #define	SSP_CMD0_CMD_MMC_GO_IDLE_STATE		0x00
> diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h
> index 9e19aabf114a..83ac268f70c0 100644
> --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h
> +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h
> @@ -17,16 +17,7 @@
>  struct mxs_timrot_regs {
>  	mxs_reg_32(hw_timrot_rotctrl)
>  	mxs_reg_32(hw_timrot_rotcount)
> -#if defined(CONFIG_MX23)
> -	mxs_reg_32(hw_timrot_timctrl0)
> -	mxs_reg_32(hw_timrot_timcount0)
> -	mxs_reg_32(hw_timrot_timctrl1)
> -	mxs_reg_32(hw_timrot_timcount1)
> -	mxs_reg_32(hw_timrot_timctrl2)
> -	mxs_reg_32(hw_timrot_timcount2)
> -	mxs_reg_32(hw_timrot_timctrl3)
> -	mxs_reg_32(hw_timrot_timcount3)
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	mxs_reg_32(hw_timrot_timctrl0)
>  	mxs_reg_32(hw_timrot_running_count0)
>  	mxs_reg_32(hw_timrot_fixed_count0)
> @@ -68,9 +59,7 @@ struct mxs_timrot_regs {
>  #define	TIMROT_ROTCTRL_OVERSAMPLE_1X			(0x3 << 10)
>  #define	TIMROT_ROTCTRL_POLARITY_B			(1 << 9)
>  #define	TIMROT_ROTCTRL_POLARITY_A			(1 << 8)
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_ROTCTRL_SELECT_B_MASK			(0x7 << 4)
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	TIMROT_ROTCTRL_SELECT_B_MASK			(0xf << 4)
>  #endif
>  #define	TIMROT_ROTCTRL_SELECT_B_OFFSET			4
> @@ -80,19 +69,14 @@ struct mxs_timrot_regs {
>  #define	TIMROT_ROTCTRL_SELECT_B_PWM2			(0x3 << 4)
>  #define	TIMROT_ROTCTRL_SELECT_B_PWM3			(0x4 << 4)
>  #define	TIMROT_ROTCTRL_SELECT_B_PWM4			(0x5 << 4)
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_ROTCTRL_SELECT_B_ROTARYA		(0x6 << 4)
> -#define	TIMROT_ROTCTRL_SELECT_B_ROTARYB		(0x7 << 4)
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	TIMROT_ROTCTRL_SELECT_B_PWM5			(0x6 << 4)
>  #define	TIMROT_ROTCTRL_SELECT_B_PWM6			(0x7 << 4)
>  #define	TIMROT_ROTCTRL_SELECT_B_PWM7			(0x8 << 4)
>  #define	TIMROT_ROTCTRL_SELECT_B_ROTARYA			(0x9 << 4)
>  #define	TIMROT_ROTCTRL_SELECT_B_ROTARYB			(0xa << 4)
>  #endif
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_ROTCTRL_SELECT_A_MASK			0x7
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	TIMROT_ROTCTRL_SELECT_A_MASK			0xf
>  #endif
>  #define	TIMROT_ROTCTRL_SELECT_A_OFFSET			0
> @@ -102,10 +86,7 @@ struct mxs_timrot_regs {
>  #define	TIMROT_ROTCTRL_SELECT_A_PWM2			0x3
>  #define	TIMROT_ROTCTRL_SELECT_A_PWM3			0x4
>  #define	TIMROT_ROTCTRL_SELECT_A_PWM4			0x5
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_ROTCTRL_SELECT_A_ROTARYA		0x6
> -#define	TIMROT_ROTCTRL_SELECT_A_ROTARYB		0x7
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	TIMROT_ROTCTRL_SELECT_A_PWM5			0x6
>  #define	TIMROT_ROTCTRL_SELECT_A_PWM6			0x7
>  #define	TIMROT_ROTCTRL_SELECT_A_PWM7			0x8
> @@ -138,15 +119,7 @@ struct mxs_timrot_regs {
>  #define	TIMROT_TIMCTRLn_SELECT_PWM2			0x3
>  #define	TIMROT_TIMCTRLn_SELECT_PWM3			0x4
>  #define	TIMROT_TIMCTRLn_SELECT_PWM4			0x5
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_TIMCTRLn_SELECT_ROTARYA		0x6
> -#define	TIMROT_TIMCTRLn_SELECT_ROTARYB		0x7
> -#define	TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL		0x8
> -#define	TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL		0x9
> -#define	TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL		0xa
> -#define	TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL		0xb
> -#define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xc
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	TIMROT_TIMCTRLn_SELECT_PWM5			0x6
>  #define	TIMROT_TIMCTRLn_SELECT_PWM6			0x7
>  #define	TIMROT_TIMCTRLn_SELECT_PWM7			0x8
> @@ -159,18 +132,12 @@ struct mxs_timrot_regs {
>  #define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xf
>  #endif
>  
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	(0xffff << 16)
> -#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	16
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	0xffffffff
>  #define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	0
>  #endif
>  
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffff
> -#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffffffff
>  #define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
>  #endif
> @@ -188,15 +155,7 @@ struct mxs_timrot_regs {
>  #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2		(0x3 << 16)
>  #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3		(0x4 << 16)
>  #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4		(0x5 << 16)
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA		(0x6 << 16)
> -#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB		(0x7 << 16)
> -#define	TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL		(0x8 << 16)
> -#define	TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL		(0x9 << 16)
> -#define	TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL		(0xa << 16)
> -#define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xb << 16)
> -#define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xc << 16)
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5		(0x6 << 16)
>  #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6		(0x7 << 16)
>  #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7		(0x8 << 16)
> @@ -208,45 +167,7 @@ struct mxs_timrot_regs {
>  #define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xe << 16)
>  #define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xf << 16)
>  #endif
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_TIMCTRL3_IRQ				(1 << 15)
> -#define	TIMROT_TIMCTRL3_IRQ_EN				(1 << 14)
> -#define	TIMROT_TIMCTRL3_DUTU_VALID			(1 << 10)
> -#endif
>  #define	TIMROT_TIMCTRL3_DUTY_CYCLE			(1 << 9)
> -#if defined(CONFIG_MX23)
> -#define	TIMROT_TIMCTRL3_POLARITY_MASK			(0x1 << 8)
> -#define	TIMROT_TIMCTRL3_POLARITY_OFFSET		8
> -#define	TIMROT_TIMCTRL3_POLARITY_POSITIVE		(0x0 << 8)
> -#define	TIMROT_TIMCTRL3_POLARITY_NEGATIVE		(0x1 << 8)
> -#define	TIMROT_TIMCTRL3_UPDATE				(1 << 7)
> -#define	TIMROT_TIMCTRL3_RELOAD				(1 << 6)
> -#define	TIMROT_TIMCTRL3_PRESCALE_MASK			(0x3 << 4)
> -#define	TIMROT_TIMCTRL3_PRESCALE_OFFSET		4
> -#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1		(0x0 << 4)
> -#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2		(0x1 << 4)
> -#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4		(0x2 << 4)
> -#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8		(0x3 << 4)
> -#define	TIMROT_TIMCTRL3_SELECT_MASK			0xf
> -#define	TIMROT_TIMCTRL3_SELECT_OFFSET			0
> -#define	TIMROT_TIMCTRL3_SELECT_NEVER_TICK		0x0
> -#define	TIMROT_TIMCTRL3_SELECT_PWM0			0x1
> -#define	TIMROT_TIMCTRL3_SELECT_PWM1			0x2
> -#define	TIMROT_TIMCTRL3_SELECT_PWM2			0x3
> -#define	TIMROT_TIMCTRL3_SELECT_PWM3			0x4
> -#define	TIMROT_TIMCTRL3_SELECT_PWM4			0x5
> -#define	TIMROT_TIMCTRL3_SELECT_ROTARYA		0x6
> -#define	TIMROT_TIMCTRL3_SELECT_ROTARYB		0x7
> -#define	TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL		0x8
> -#define	TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL		0x9
> -#define	TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL		0xa
> -#define	TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL		0xb
> -#define	TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS		0xc
> -#define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK	(0xffff << 16)
> -#define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET	16
> -#define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK	0xffff
> -#define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET	0
> -#endif
>  
>  #define	TIMROT_VERSION_MAJOR_MASK			(0xff << 24)
>  #define	TIMROT_VERSION_MAJOR_OFFSET			24
> diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
> index 20ee863ac7e7..5d86d6b28312 100644
> --- a/arch/arm/include/asm/arch-mxs/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
> @@ -16,9 +16,7 @@ int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int),
>  
>  #ifdef CONFIG_SPL_BUILD
>  
> -#if defined(CONFIG_MX23)
> -#include <asm/arch/iomux-mx23.h>
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #include <asm/arch/iomux-mx28.h>
>  #endif
>  
> @@ -36,18 +34,7 @@ struct mxs_pair {
>  };
>  
>  static const struct mxs_pair mxs_boot_modes[] = {
> -#if defined(CONFIG_MX23)
> -	{ 0x00, 0x0f, "USB" },
> -	{ 0x01, 0x1f, "I2C, master" },
> -	{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
> -	{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
> -	{ 0x04, 0x1f, "NAND" },
> -	{ 0x06, 0x1f, "JTAG" },
> -	{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
> -	{ 0x09, 0x1f, "SSP SD/MMC #0" },
> -	{ 0x0a, 0x1f, "SSP SD/MMC #1" },
> -	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	{ 0x00, 0x0f, "USB #0" },
>  	{ 0x01, 0x1f, "I2C #0, master, 3V3" },
>  	{ 0x11, 0x1f, "I2C #0, master, 1V8" },
> diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h
> index 55eb84cb8e7e..30a0fc057f2a 100644
> --- a/arch/arm/include/asm/mach-imx/dma.h
> +++ b/arch/arm/include/asm/mach-imx/dma.h
> @@ -23,19 +23,7 @@
>  /*
>   * MXS DMA channels
>   */
> -#if defined(CONFIG_MX23)
> -enum {
> -	MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
> -	MXS_DMA_CHANNEL_AHB_APBH_SSP0,
> -	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
> -	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
> -	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
> -	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
> -	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
> -	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
> -	MXS_MAX_DMA_CHANNELS,
> -};
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  enum {
>  	MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
>  	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
> diff --git a/arch/arm/include/asm/mach-imx/regs-apbh.h b/arch/arm/include/asm/mach-imx/regs-apbh.h
> index 94c330c7f928..c751eab99164 100644
> --- a/arch/arm/include/asm/mach-imx/regs-apbh.h
> +++ b/arch/arm/include/asm/mach-imx/regs-apbh.h
> @@ -17,86 +17,6 @@
>  
>  #ifndef	__ASSEMBLY__
>  
> -#if defined(CONFIG_MX23)
> -struct mxs_apbh_regs {
> -	mxs_reg_32(hw_apbh_ctrl0)
> -	mxs_reg_32(hw_apbh_ctrl1)
> -	mxs_reg_32(hw_apbh_ctrl2)
> -	mxs_reg_32(hw_apbh_channel_ctrl)
> -
> -	union {
> -	struct {
> -		mxs_reg_32(hw_apbh_ch_curcmdar)
> -		mxs_reg_32(hw_apbh_ch_nxtcmdar)
> -		mxs_reg_32(hw_apbh_ch_cmd)
> -		mxs_reg_32(hw_apbh_ch_bar)
> -		mxs_reg_32(hw_apbh_ch_sema)
> -		mxs_reg_32(hw_apbh_ch_debug1)
> -		mxs_reg_32(hw_apbh_ch_debug2)
> -	} ch[8];
> -	struct {
> -		mxs_reg_32(hw_apbh_ch0_curcmdar)
> -		mxs_reg_32(hw_apbh_ch0_nxtcmdar)
> -		mxs_reg_32(hw_apbh_ch0_cmd)
> -		mxs_reg_32(hw_apbh_ch0_bar)
> -		mxs_reg_32(hw_apbh_ch0_sema)
> -		mxs_reg_32(hw_apbh_ch0_debug1)
> -		mxs_reg_32(hw_apbh_ch0_debug2)
> -		mxs_reg_32(hw_apbh_ch1_curcmdar)
> -		mxs_reg_32(hw_apbh_ch1_nxtcmdar)
> -		mxs_reg_32(hw_apbh_ch1_cmd)
> -		mxs_reg_32(hw_apbh_ch1_bar)
> -		mxs_reg_32(hw_apbh_ch1_sema)
> -		mxs_reg_32(hw_apbh_ch1_debug1)
> -		mxs_reg_32(hw_apbh_ch1_debug2)
> -		mxs_reg_32(hw_apbh_ch2_curcmdar)
> -		mxs_reg_32(hw_apbh_ch2_nxtcmdar)
> -		mxs_reg_32(hw_apbh_ch2_cmd)
> -		mxs_reg_32(hw_apbh_ch2_bar)
> -		mxs_reg_32(hw_apbh_ch2_sema)
> -		mxs_reg_32(hw_apbh_ch2_debug1)
> -		mxs_reg_32(hw_apbh_ch2_debug2)
> -		mxs_reg_32(hw_apbh_ch3_curcmdar)
> -		mxs_reg_32(hw_apbh_ch3_nxtcmdar)
> -		mxs_reg_32(hw_apbh_ch3_cmd)
> -		mxs_reg_32(hw_apbh_ch3_bar)
> -		mxs_reg_32(hw_apbh_ch3_sema)
> -		mxs_reg_32(hw_apbh_ch3_debug1)
> -		mxs_reg_32(hw_apbh_ch3_debug2)
> -		mxs_reg_32(hw_apbh_ch4_curcmdar)
> -		mxs_reg_32(hw_apbh_ch4_nxtcmdar)
> -		mxs_reg_32(hw_apbh_ch4_cmd)
> -		mxs_reg_32(hw_apbh_ch4_bar)
> -		mxs_reg_32(hw_apbh_ch4_sema)
> -		mxs_reg_32(hw_apbh_ch4_debug1)
> -		mxs_reg_32(hw_apbh_ch4_debug2)
> -		mxs_reg_32(hw_apbh_ch5_curcmdar)
> -		mxs_reg_32(hw_apbh_ch5_nxtcmdar)
> -		mxs_reg_32(hw_apbh_ch5_cmd)
> -		mxs_reg_32(hw_apbh_ch5_bar)
> -		mxs_reg_32(hw_apbh_ch5_sema)
> -		mxs_reg_32(hw_apbh_ch5_debug1)
> -		mxs_reg_32(hw_apbh_ch5_debug2)
> -		mxs_reg_32(hw_apbh_ch6_curcmdar)
> -		mxs_reg_32(hw_apbh_ch6_nxtcmdar)
> -		mxs_reg_32(hw_apbh_ch6_cmd)
> -		mxs_reg_32(hw_apbh_ch6_bar)
> -		mxs_reg_32(hw_apbh_ch6_sema)
> -		mxs_reg_32(hw_apbh_ch6_debug1)
> -		mxs_reg_32(hw_apbh_ch6_debug2)
> -		mxs_reg_32(hw_apbh_ch7_curcmdar)
> -		mxs_reg_32(hw_apbh_ch7_nxtcmdar)
> -		mxs_reg_32(hw_apbh_ch7_cmd)
> -		mxs_reg_32(hw_apbh_ch7_bar)
> -		mxs_reg_32(hw_apbh_ch7_sema)
> -		mxs_reg_32(hw_apbh_ch7_debug1)
> -		mxs_reg_32(hw_apbh_ch7_debug2)
> -	};
> -	};
> -	mxs_reg_32(hw_apbh_version)
> -};
> -
> -#else
>  struct mxs_apbh_regs {
>  	mxs_reg_32(hw_apbh_ctrl0)
>  	mxs_reg_32(hw_apbh_ctrl1)
> @@ -235,7 +155,6 @@ struct mxs_apbh_regs {
>  	};
>  	mxs_reg_32(hw_apbh_version)
>  };
> -#endif
>  
>  #endif
>  
> @@ -243,20 +162,7 @@ struct mxs_apbh_regs {
>  #define	APBH_CTRL0_CLKGATE				(1 << 30)
>  #define	APBH_CTRL0_AHB_BURST8_EN			(1 << 29)
>  #define	APBH_CTRL0_APB_BURST_EN				(1 << 28)
> -#if defined(CONFIG_MX23)
> -#define	APBH_CTRL0_RSVD0_MASK				(0xf << 24)
> -#define	APBH_CTRL0_RSVD0_OFFSET				24
> -#define	APBH_CTRL0_RESET_CHANNEL_MASK			(0xff << 16)
> -#define	APBH_CTRL0_RESET_CHANNEL_OFFSET			16
> -#define	APBH_CTRL0_CLKGATE_CHANNEL_MASK			(0xff << 8)
> -#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		8
> -#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP0			0x02
> -#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP1			0x04
> -#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x10
> -#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x20
> -#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x40
> -#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x80
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	APBH_CTRL0_RSVD0_MASK				(0xfff << 16)
>  #define	APBH_CTRL0_RSVD0_OFFSET				16
>  #define	APBH_CTRL0_CLKGATE_CHANNEL_MASK			0xffff
> @@ -393,24 +299,7 @@ struct mxs_apbh_regs {
>  /* Not on i.MX23 */
>  #define	APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET		16
>  
> -#if defined(CONFIG_MX23)
> -#define	APBH_DEVSEL_CH7_MASK				(0xf << 28)
> -#define	APBH_DEVSEL_CH7_OFFSET				28
> -#define	APBH_DEVSEL_CH6_MASK				(0xf << 24)
> -#define	APBH_DEVSEL_CH6_OFFSET				24
> -#define	APBH_DEVSEL_CH5_MASK				(0xf << 20)
> -#define	APBH_DEVSEL_CH5_OFFSET				20
> -#define	APBH_DEVSEL_CH4_MASK				(0xf << 16)
> -#define	APBH_DEVSEL_CH4_OFFSET				16
> -#define	APBH_DEVSEL_CH3_MASK				(0xf << 12)
> -#define	APBH_DEVSEL_CH3_OFFSET				12
> -#define	APBH_DEVSEL_CH2_MASK				(0xf << 8)
> -#define	APBH_DEVSEL_CH2_OFFSET				8
> -#define	APBH_DEVSEL_CH1_MASK				(0xf << 4)
> -#define	APBH_DEVSEL_CH1_OFFSET				4
> -#define	APBH_DEVSEL_CH0_MASK				(0xf << 0)
> -#define	APBH_DEVSEL_CH0_OFFSET				0
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define	APBH_DEVSEL_CH15_MASK				(0x3 << 30)
>  #define	APBH_DEVSEL_CH15_OFFSET				30
>  #define	APBH_DEVSEL_CH14_MASK				(0x3 << 28)
> diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h
> index 587463879661..12e0faad91d6 100644
> --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
> +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
> @@ -29,10 +29,6 @@ struct mxs_lcdif_regs {
>  	mxs_reg_32(hw_lcdif_cur_buf)		/* 0x30/0x40 */
>  	mxs_reg_32(hw_lcdif_next_buf)		/* 0x40/0x50 */
>  
> -#if defined(CONFIG_MX23)
> -	uint32_t	reserved1[4];
> -#endif
> -
>  	mxs_reg_32(hw_lcdif_timing)		/* 0x60 */
>  	mxs_reg_32(hw_lcdif_vdctrl0)		/* 0x70 */
>  	mxs_reg_32(hw_lcdif_vdctrl1)		/* 0x80 */
> @@ -52,9 +48,6 @@ struct mxs_lcdif_regs {
>  	mxs_reg_32(hw_lcdif_csc_offset)		/* 0x160 */
>  	mxs_reg_32(hw_lcdif_csc_limit)		/* 0x170 */
>  
> -#if defined(CONFIG_MX23)
> -	uint32_t	reserved2[12];
> -#endif
>  	mxs_reg_32(hw_lcdif_data)		/* 0x1b0/0x180 */
>  	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x1c0/0x190 */
>  #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
> @@ -214,13 +207,8 @@ struct mxs_lcdif_regs {
>  #define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK				0xffffffff
>  #define	LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET			0
>  
> -#if defined(CONFIG_MX23)
> -#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0xff << 24)
> -#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			24
> -#else
>  #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0x3fff << 18)
>  #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			18
> -#endif
>  #define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK				0x3ffff
>  #define	LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET			0
>  
> diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig
> index bd075de2b826..e04b0dc10f6c 100644
> --- a/arch/arm/mach-imx/mxs/Kconfig
> +++ b/arch/arm/mach-imx/mxs/Kconfig
> @@ -1,24 +1,3 @@
> -if ARCH_MX23
> -
> -config MX23
> -	bool
> -	default y
> -
> -choice
> -	prompt "MX23 board select"
> -	optional
> -
> -config TARGET_SANSA_FUZE_PLUS
> -	bool "Support sansa_fuze_plus"
> -
> -endchoice
> -
> -config SYS_SOC
> -	default "mxs"
> -
> -
> -endif
> -
>  if ARCH_MX28
>  
>  config MX28
> diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
> index da988f6bb667..e05415d2d502 100644
> --- a/drivers/dma/apbh_dma.c
> +++ b/drivers/dma/apbh_dma.c
> @@ -215,10 +215,7 @@ static int mxs_dma_reset(int channel)
>  	struct mxs_apbh_regs *apbh_regs =
>  		(struct mxs_apbh_regs *)MXS_APBH_BASE;
>  	int ret;
> -#if defined(CONFIG_MX23)
> -	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
> -	uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
> -#elif defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
> +#if defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
>  	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
>  	u32 setreg = (uintptr_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
>  	u32 offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
> diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
> index 4b2b18fdb538..22e50dd21ca9 100644
> --- a/drivers/gpio/mxs_gpio.c
> +++ b/drivers/gpio/mxs_gpio.c
> @@ -15,15 +15,7 @@
>  #include <asm/arch/iomux.h>
>  #include <asm/arch/imx-regs.h>
>  
> -#if	defined(CONFIG_MX23)
> -#define	PINCTRL_BANKS		3
> -#define	PINCTRL_DOUT(n)		(0x0500 + ((n) * 0x10))
> -#define	PINCTRL_DIN(n)		(0x0600 + ((n) * 0x10))
> -#define	PINCTRL_DOE(n)		(0x0700 + ((n) * 0x10))
> -#define	PINCTRL_PIN2IRQ(n)	(0x0800 + ((n) * 0x10))
> -#define	PINCTRL_IRQEN(n)	(0x0900 + ((n) * 0x10))
> -#define	PINCTRL_IRQSTAT(n)	(0x0c00 + ((n) * 0x10))
> -#elif	defined(CONFIG_MX28)
> +#if	defined(CONFIG_MX28)
>  #define	PINCTRL_BANKS		5
>  #define	PINCTRL_DOUT(n)		(0x0700 + ((n) * 0x10))
>  #define	PINCTRL_DIN(n)		(0x0900 + ((n) * 0x10))
> @@ -32,7 +24,7 @@
>  #define	PINCTRL_IRQEN(n)	(0x1100 + ((n) * 0x10))
>  #define	PINCTRL_IRQSTAT(n)	(0x1400 + ((n) * 0x10))
>  #else
> -#error "Please select CONFIG_MX23 or CONFIG_MX28"
> +#error "Please select CONFIG_MX28"
>  #endif
>  
>  #define GPIO_INT_FALL_EDGE	0x0
> diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
> index 8fd41764152f..863e67f10c52 100644
> --- a/drivers/mmc/mxsmmc.c
> +++ b/drivers/mmc/mxsmmc.c
> @@ -391,15 +391,7 @@ mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
>  		ctrl0 |= SSP_CTRL0_DATA_XFER;
>  
>  		reg = data->blocksize * data->blocks;
> -#if defined(CONFIG_MX23)
> -		ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
> -
> -		clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
> -			SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
> -			((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
> -			((ffs(data->blocksize) - 1) <<
> -				SSP_CMD0_BLOCK_SIZE_OFFSET));
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  		writel(reg, &ssp_regs->hw_ssp_xfer_size);
>  
>  		reg = ((data->blocks - 1) <<
> @@ -595,8 +587,6 @@ static int mxsmmc_probe(struct udevice *dev)
>  
>  #ifdef CONFIG_MX28
>  	priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0;
> -#else /* CONFIG_MX23 */
> -	priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0;
>  #endif
>  	mmc = &plat->mmc;
>  	mmc->cfg = &plat->cfg;
> diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
> index d41352a0bb8c..45b541fe1668 100644
> --- a/drivers/spi/mxs_spi.c
> +++ b/drivers/spi/mxs_spi.c
> @@ -83,10 +83,7 @@ static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
>  
>  	while (length--) {
>  		/* We transfer 1 byte */
> -#if defined(CONFIG_MX23)
> -		writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
> -		writel(1, &ssp_regs->hw_ssp_ctrl0_set);
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  		writel(1, &ssp_regs->hw_ssp_xfer_size);
>  #endif
>  
> @@ -146,9 +143,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
>  	int tl;
>  	int ret = 0;
>  
> -#if defined(CONFIG_MX23)
> -	const int mxs_spi_pio_words = 1;
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  	const int mxs_spi_pio_words = 4;
>  #endif
>  
> diff --git a/include/configs/mxs.h b/include/configs/mxs.h
> index 325c3ee00ce3..3db3e18066e7 100644
> --- a/include/configs/mxs.h
> +++ b/include/configs/mxs.h
> @@ -23,17 +23,9 @@
>   * Includes
>   */
>  
> -#if defined(CONFIG_MX23) && defined(CONFIG_MX28)
> -#error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
> -#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
> -#error Select one of CONFIG_MX23 or CONFIG_MX28 !
> -#endif
> -
>  #include <asm/arch/regs-base.h>
>  
> -#if defined(CONFIG_MX23)
> -#include <asm/arch/iomux-mx23.h>
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #include <asm/arch/iomux-mx28.h>
>  #endif
>  
> @@ -54,9 +46,7 @@
>  
>  /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
>  #define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
> -#if defined(CONFIG_MX23)
> -#define CONFIG_SYS_INIT_RAM_SIZE	(32 * 1024)
> -#elif defined(CONFIG_MX28)
> +#if defined(CONFIG_MX28)
>  #define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
>  #endif
>  
> diff --git a/tools/Makefile b/tools/Makefile
> index 2d550432ba5a..ce8faeb85249 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -127,7 +127,7 @@ fit_info-objs   := $(dumpimage-mkimage-objs) fit_info.o
>  fit_check_sign-objs   := $(dumpimage-mkimage-objs) fit_check_sign.o
>  file2include-objs := file2include.o
>  
> -ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),)
> +ifneq ($(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),)
>  # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
>  # the mxsimage support within tools/mxsimage.c .
>  HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS
> @@ -155,7 +155,7 @@ HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE
>  endif
>  
>  # MXSImage needs LibSSL
> -ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),)
> +ifneq ($(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),)
>  HOSTCFLAGS_kwbimage.o += \
>  	$(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "")
>  HOSTLDLIBS_mkimage += \
> @@ -186,7 +186,6 @@ hostprogs-$(CONFIG_X86) += ifdtool
>  ifwitool-objs := ifwitool.o
>  hostprogs-$(CONFIG_X86)$(CONFIG_SANDBOX) += ifwitool
>  
> -hostprogs-$(CONFIG_MX23) += mxsboot
>  hostprogs-$(CONFIG_MX28) += mxsboot
>  HOSTCFLAGS_mxsboot.o := -pedantic
>  
> 


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================




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