[v3 00/17] Add Intel N5X SoC support
Siew Chin Lim
elly.siew.chin.lim at intel.com
Sun Jun 13 10:48:35 CEST 2021
This is the 3rd version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot without ATF for debugging purpose,
ATF boot, and ATF boot with VAB enabled.
[1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Patch status:
Have changes: Patch 4, 5, 7, 12, 15
Other patches unchanged.
Detail changelog can find in commit message.
v2->v3:
--------
Patch 4:
- Adding helper function for getting endianness type.
Patch 5:
- Use BIT() macro for CLKMGR_INTER_*_MASK macro
Patch 7:
- Use BIT() and GENMASK() macro for all *MASK macro
Patch 12:
- Sorting header
- Used prefix OPM_xxx
- Simplify the code with do...while loop.
- Created common function for processing handoff
- Adding function of calibration data feedback to LPDDR4 controllers
Patch 15:
- Update comment for memory example code
- Move all common dts settings for N5X from
socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi
- Remove unused parameter "u-boot,boot0"
History:
--------
[v1] https://patchwork.ozlabs.org/project/uboot/cover/20210331143908.48211-1-elly.siew.chin.lim@intel.com/
[v2] https://patchwork.ozlabs.org/project/uboot/cover/20210430073814.193576-1-elly.siew.chin.lim@intel.com/
Siew Chin Lim (14):
arm: socfpga: Move linux_qspi_enable from bootcommand to
board_prep_linux function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
drivers: clk: Add clock driver for Intel N5X device
arm: socfpga: Get clock manager base address for Intel N5X device
drivers: clk: Add memory clock driver for Intel N5X device
arm: socfpga: Move cm_get_mpu_clk_hz function declaration to
clock_manager.h
arm: socfpga: Add clock manager for Intel N5X device
arm: socfpga: Changed misc_s10.c to misc_soc64.c
arm: socfpga: Add SPL for Intel N5X device
board: intel: Add socdk board support for Intel N5X device
arm: dts: Add base dtsi and devkit dts for Intel N5X device
include: configs: Add Intel N5X device CONFIGs
arm: socfpga: Enable Intel N5X device build
Tien Fong Chee (3):
arm: socfpga: Add handoff data support for Intel N5X device
ddr: socfpga: Enable memory test on memory size less than 1GB
ddr: altera: Add SDRAM driver for Intel N5X device
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 175 ++
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67 +
arch/arm/dts/socfpga_n5x_socdk.dts | 154 ++
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile | 32 +-
arch/arm/mach-socfpga/board.c | 17 +-
arch/arm/mach-socfpga/clock_manager_n5x.c | 80 +
.../{base_addr_s10.h => base_addr_soc64.h} | 11 +-
.../mach-socfpga/include/mach/clock_manager.h | 3 +
.../include/mach/clock_manager_agilex.h | 2 -
.../include/mach/clock_manager_arria10.h | 1 -
.../include/mach/clock_manager_gen5.h | 1 -
.../include/mach/clock_manager_n5x.h | 12 +
.../include/mach/clock_manager_s10.h | 1 -
arch/arm/mach-socfpga/include/mach/firewall.h | 6 +
.../mach-socfpga/include/mach/handoff_soc64.h | 38 +-
.../include/mach/system_manager_soc64.h | 10 +-
arch/arm/mach-socfpga/misc.c | 3 +
.../mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +-
arch/arm/mach-socfpga/spl_n5x.c | 94 +
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +-
board/intel/n5x-socdk/MAINTAINERS | 7 +
board/intel/n5x-socdk/Makefile | 7 +
board/intel/n5x-socdk/socfpga.c | 7 +
configs/socfpga_agilex_atf_defconfig | 2 +-
...tf_defconfig => socfpga_n5x_atf_defconfig} | 13 +-
...ex_atf_defconfig => socfpga_n5x_defconfig} | 29 +-
...tf_defconfig => socfpga_n5x_vab_defconfig} | 14 +-
configs/socfpga_stratix10_atf_defconfig | 2 +-
drivers/clk/altera/Makefile | 4 +-
drivers/clk/altera/clk-mem-n5x.c | 136 +
drivers/clk/altera/clk-mem-n5x.h | 84 +
drivers/clk/altera/clk-n5x.c | 489 ++++
drivers/clk/altera/clk-n5x.h | 217 ++
drivers/ddr/altera/Makefile | 3 +-
drivers/ddr/altera/sdram_n5x.c | 2298 +++++++++++++++++
drivers/ddr/altera/sdram_soc64.c | 94 +-
drivers/ddr/altera/sdram_soc64.h | 1 +
include/configs/socfpga_n5x_socdk.h | 45 +
include/configs/socfpga_soc64_common.h | 2 +-
include/dt-bindings/clock/n5x-clock.h | 71 +
43 files changed, 4296 insertions(+), 120 deletions(-)
create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts
create mode 100644 arch/arm/mach-socfpga/clock_manager_n5x.c
rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} (85%)
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%)
create mode 100644 arch/arm/mach-socfpga/spl_n5x.c
create mode 100644 board/intel/n5x-socdk/MAINTAINERS
create mode 100644 board/intel/n5x-socdk/Makefile
create mode 100644 board/intel/n5x-socdk/socfpga.c
copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_atf_defconfig} (83%)
copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_defconfig} (63%)
copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_vab_defconfig} (82%)
create mode 100644 drivers/clk/altera/clk-mem-n5x.c
create mode 100644 drivers/clk/altera/clk-mem-n5x.h
create mode 100644 drivers/clk/altera/clk-n5x.c
create mode 100644 drivers/clk/altera/clk-n5x.h
create mode 100644 drivers/ddr/altera/sdram_n5x.c
create mode 100644 include/configs/socfpga_n5x_socdk.h
create mode 100644 include/dt-bindings/clock/n5x-clock.h
--
2.19.0
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