[PATCH v5 2/5] common: board_r: support enable_caches for RISC-V

[Zong Li]

The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V

Signed-off-by: Zong Li <zong.li at sifive.com>
---
 arch/riscv/lib/cache.c | 4 ++++
 common/board_r.c       | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index b1d42bcc2b..686e699efb 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -70,3 +70,7 @@ __weak int dcache_status(void)
 {
 	return 0;
 }
+
+__weak void enable_caches(void)
+{
+}
diff --git a/common/board_r.c b/common/board_r.c
index e3e6248a1f..630c2451a2 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -114,7 +114,7 @@ static int initr_reloc(void)
 	return 0;
 }
 
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
 /*
  * Some of these functions are needed purely because the functions they
  * call return void. If we change them to return 0, these stubs can go away.
@@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
 	initr_trace,
 	initr_reloc,
 	/* TODO: could x86/PPC have this also perhaps? */
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
 	initr_caches,
 	/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
 	 *	 A temporary mapping of IFC high region is since removed,
-- 
2.32.0