[PATCH v5 2/5] common: board_r: support enable_caches for RISC-V

[Rick Chen]

> From: Zong Li <zong.li at sifive.com>
> Sent: Wednesday, September 01, 2021 3:02 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang at andestech.com>; bmeng.cn at gmail.com; seanga2 at gmail.com; green.wan at sifive.com; paul.walmsley at sifive.com; sjg at chromium.org; u-boot at lists.denx.de
> Cc: Zong Li <zong.li at sifive.com>
> Subject: [PATCH v5 2/5] common: board_r: support enable_caches for RISC-V
>
> The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V
>
> Signed-off-by: Zong Li <zong.li at sifive.com>
> ---
>  arch/riscv/lib/cache.c | 4 ++++
>  common/board_r.c       | 4 ++--
>  2 files changed, 6 insertions(+), 2 deletions(-)

Reviewed-by: Rick Chen <rick at andestech.com>