[PATCH v2 8/9] arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux

[Vladimir Oltean]

On Wed, Sep 01, 2021 at 10:55:21AM +0200, Michael Walle wrote:
> -		pcie1: pcie at 3400000 {
> -			   ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
> -				   0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> -		};
>  
> -		pcie2: pcie at 3500000 {
> -			   ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
> -				   0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> -		};
> +		pcie1: pcie at 3400000 {
> +			ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000   /* downstream I/O */
> +				  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
>  		};
>  
> +		pcie2: pcie at 3500000 {
> +			ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000   /* downstream I/O */
> +				  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> +		};

This change also makes an undocumented movement of the PCIe window in
the SoC memory space from 0x80_00020000 to 0x80_00010000 for pcie1, and
from 0x88_00020000 to 0x88_00010000 for pcie2.

It should probably work either way, considering that the SoC system
memory map lists the entire 32GB of address space starting from
0x0080_0000_0000 as belonging to PEX1, and 0x0088_0000_0000 belonging to
PEX2, but either way, is there no better way to make these changes?!
It seems like a lot to go through. At the very least do document the
changes in the commit message, it makes you be aware of what you're
changing, and it makes people get an overview instead of needing to do
dumpster diving.