[PATCH] sunxi: mmc: A20: Fix MMC optimisation

[Andre Przywara]

Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the
FIFO is completely full: the level size reads as zero, but the FIFO_FULL
bit is set. We won't do a single iteration of the read loop in this
case, so will be stuck forever.

Check for this situation and use a safe minimal FIFO size instead when
we hit this case.

This fixes MMC boot on A20 devices after the MMC FIFO optimisation
(9faae5457f52).

Signed-off-by: Andre Przywara <andre.przywara at arm.com>
---
 drivers/mmc/sunxi_mmc.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 178b8cf106..aaab0cf866 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -349,10 +349,14 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 		 * register without checking the status register after every
 		 * read. That saves half of the costly MMIO reads, effectively
 		 * doubling the read performance.
+		 * Some SoCs (A20) report a level of 0 if the FIFO is
+		 * completely full (value masked out?). Use a safe minimal
+		 * FIFO size in this case.
 		 */
-		for (in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
-		     in_fifo > 0;
-		     in_fifo--)
+		in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
+		if (in_fifo == 0 && (status & SUNXI_MMC_STATUS_FIFO_FULL))
+			in_fifo = 32;
+		for (; in_fifo > 0; in_fifo--)
 			buff[i++] = readl_relaxed(&priv->reg->fifo);
 		dmb();
 	}
-- 
2.17.1