Running qemu tests on RISC-V

[Michael Lawnick]

Hi Simon,

having absolutely no knowledge about the details here just 2 cents:
It looks like concurrent run of multiple cores. Are you sure that all
cores beside #0 are properly caught and blocked on start?

KR
Michael

Am 07.02.2022 um 16:38 schrieb Simon Glass:
> Hi,
>
> I am trying to run the SPL tests for riscv32 but it dies with an
> illegal instruction. I have tried building qemu 4.2 but it seems to
> happen on various versions. Has anyone seen this?
>
>
> +u-boot-test-reset qemu-riscv32_spl na
>
> U-Boot SPL 2022.01 (Feb 07 2022 - 08:33:30 -0700)
> Trying to boot from RAM
> Unhandled exception: Illegal instruction
> EPC: 8UUU1000564nhandled nhandled exception:nhandled exceptexception:
> ion:  RA: 810000IIllegal10 instruction
> Illllegal inegal instruction
> EPC: structEPC: ion
> EPC:  TVAL: 81081000564 RA: 008100564 RA: 8100000100010 TVAL: 00000000 TV
> 0000000
> AL: 00
> ode:00000
>
> Code:3400
> 050 808334004082 0073 00 8081050 2 bff5 0001 55b7007 4942 ( 3 859b 134f5)
> 2 0073 bff5
> 0
> 001 1050 bff5 055b7 001 55b74942  4942 ((859b 859b 34f34f5)
> 5)
>
>
>
>
> 81000564 RA: 81000010 TVAL: 00000000
>
> Code: 3400 8082 0073 1050 bff5 0001 55b7 4942 (859b 34f5)
>
>
> resresetting ...
> pporesetting ...ng ...
> rese
> trtered ys not supported yet
> ### ERROet
> R ### Please RES### ERRet notET the board ###
> OR ### Please  sRESEupT the board ###
> ported yet
> ### ERROR ### Please RESET the board ###
>
> Regards,
> Simon