[PATCH v2 1/2] phy: zynqmp: Add support for sata and DP phy initialization
Michal Simek
monstr at monstr.eu
Tue Feb 15 13:04:41 CET 2022
po 7. 2. 2022 v 10:36 odesílatel Michal Simek <michal.simek at xilinx.com> napsal:
>
> DP is untested but just c&p from Linux driver. Sata is tested on kv260-revA
> board which has SATA connector populated.
>
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
>
> ---
>
> Changes in v2:
> Revoke default case - reported by T Karthik Reddy
>
> drivers/phy/phy-zynqmp.c | 30 ++++++++++++++++++++++++++++--
> 1 file changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c
> index 9dc3d426a3d3..08c1b6efcfdc 100644
> --- a/drivers/phy/phy-zynqmp.c
> +++ b/drivers/phy/phy-zynqmp.c
> @@ -373,6 +373,29 @@ static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
> xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
> }
>
> +/* DP-specific initialization. */
> +static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
> +{
> + xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
> + L0_TXPMD_TM_45_OVER_DP_MAIN |
> + L0_TXPMD_TM_45_ENABLE_DP_MAIN |
> + L0_TXPMD_TM_45_OVER_DP_POST1 |
> + L0_TXPMD_TM_45_OVER_DP_POST2 |
> + L0_TXPMD_TM_45_ENABLE_DP_POST2);
> + xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
> + L0_TX_ANA_TM_118_FORCE_17_0);
> +}
> +
> +/* SATA-specific initialization. */
> +static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
> +{
> + struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
> +
> + xpsgtr_bypass_scrambler_8b10b(gtr_phy);
> +
> + writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
> +}
> +
> /* SGMII-specific initialization. */
> static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
> {
> @@ -427,9 +450,12 @@ static int xpsgtr_init(struct phy *x)
> case ICM_PROTOCOL_SGMII:
> xpsgtr_phy_init_sgmii(gtr_phy);
> break;
> - case ICM_PROTOCOL_DP:
> case ICM_PROTOCOL_SATA:
> - return -EINVAL;
> + xpsgtr_phy_init_sata(gtr_phy);
> + break;
> + case ICM_PROTOCOL_DP:
> + xpsgtr_phy_init_dp(gtr_phy);
> + break;
> }
>
> dev_dbg(gtr_dev->dev, "lane %u (type %u, protocol %u): init done\n",
> --
> 2.35.0
>
applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
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