[PATCH 2/2] ARM: imx: imx8mn-ddr4-evk: Add ethernet support

[Stefano Babic]

Hi Marek,

On 14.02.22 00:36, Marek Vasut wrote:
> Add support for ethernet on the imx8mn-ddr4-evk.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Stefano Babic <sbabic at denx.de>
> ---

I have not pushed this patch because I am puzzled. There is nothing 
wrong in the patch, and I can apply it, but CI fails randomly. There is 
a warning during compilation of this board, see:

https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/394060

However, this makes no sense. It looks like that

+       if (IS_ENABLED(CONFIG_FEC_MXC))
+               setup_fec();

This has effect, while during preprocessing of the same file:

+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)

it looks like as "deactivated", no idea why. The warning makes no sense 
by reading the code. And if I build the board locally, with  make or 
buildman, everything fine - no error at all.  But, even locally, 
"buildman aarch64" reports this warning. No idea why, but I cannot add 
this to PR else the breakage goes into Tom's tree.

Of course, if I drop #if IS_ENABLED(CONFIG_FEC_MXC), everything fine, 
but it does not means it is a solution.

Best regards,
Stefano

>   arch/arm/dts/imx8mn-evk.dtsi            |  1 +
>   board/freescale/imx8mn_evk/imx8mn_evk.c | 41 +++++++++++++++++++++++--
>   configs/imx8mn_ddr4_evk_defconfig       |  8 +++++
>   3 files changed, 47 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi
> index 76d042a4cf0..416fadb22b1 100644
> --- a/arch/arm/dts/imx8mn-evk.dtsi
> +++ b/arch/arm/dts/imx8mn-evk.dtsi
> @@ -53,6 +53,7 @@
>   	pinctrl-0 = <&pinctrl_fec1>;
>   	phy-mode = "rgmii-id";
>   	phy-handle = <&ethphy0>;
> +	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
>   	fsl,magic-packet;
>   	status = "okay";
>   
> diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c
> index 9a0a0488bf4..6979bbcbe52 100644
> --- a/board/freescale/imx8mn_evk/imx8mn_evk.c
> +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c
> @@ -7,17 +7,52 @@
>   #include <env.h>
>   #include <init.h>
>   #include <asm/global_data.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/io.h>
>   
>   DECLARE_GLOBAL_DATA_PTR;
>   
> -int board_init(void)
> +int board_mmc_get_env_dev(int devno)
> +{
> +	return devno;
> +}
> +
> +#if IS_ENABLED(CONFIG_FEC_MXC)
> +static int setup_fec(void)
>   {
> +	struct iomuxc_gpr_base_regs *gpr =
> +		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> +	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
> +	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
> +
>   	return 0;
>   }
>   
> -int board_mmc_get_env_dev(int devno)
> +int board_phy_config(struct phy_device *phydev)
>   {
> -	return devno;
> +	/* enable rgmii rxc skew and phy mode select to RGMII copper */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> +	if (phydev->drv->config)
> +		phydev->drv->config(phydev);
> +	return 0;
> +}
> +#endif
> +
> +int board_init(void)
> +{
> +	if (IS_ENABLED(CONFIG_FEC_MXC))
> +		setup_fec();
> +
> +	return 0;
>   }
>   
>   int board_late_init(void)
> diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
> index 28cc551dc41..a760709772f 100644
> --- a/configs/imx8mn_ddr4_evk_defconfig
> +++ b/configs/imx8mn_ddr4_evk_defconfig
> @@ -43,6 +43,9 @@ CONFIG_CMD_FUSE=y
>   CONFIG_CMD_GPIO=y
>   CONFIG_CMD_I2C=y
>   CONFIG_CMD_MMC=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
>   CONFIG_CMD_CACHE=y
>   CONFIG_CMD_REGULATOR=y
>   CONFIG_CMD_EXT4_WRITE=y
> @@ -67,7 +70,12 @@ CONFIG_MMC_HS400_ES_SUPPORT=y
>   CONFIG_MMC_HS400_SUPPORT=y
>   CONFIG_FSL_USDHC=y
>   CONFIG_PHYLIB=y
> +CONFIG_PHY_ATHEROS=y
>   CONFIG_DM_ETH=y
> +CONFIG_DM_ETH_PHY=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
>   CONFIG_PINCTRL=y
>   CONFIG_SPL_PINCTRL=y
>   CONFIG_PINCTRL_IMX8M=y

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