[PATCH v4] imx: support i.MX8QM DMSSE20 a1 board

Marcel Ziswiler marcel.ziswiler at toradex.com
Wed Jul 13 09:50:03 CEST 2022


Hi Oliver

On Tue, 2022-07-12 at 12:14 +0200, Oliver Graute wrote:
> Add i.MX8QM DMSSE20 a1 board support
> 
> U-Boot 2022.07-00033-g2a5cf8e9e7 (Jul 12 2022 - 11:29:05 +0200)
> 
> Model: Advantech iMX8QM DMSSE20
> Board: DMS-SE20A1 8GB
> Build: SCFW 549b1e18, SECO-FW c9de51c0, ATF 5782363
> Boot:  USB
> DRAM:  8 GiB
> Core:  100 devices, 19 uclasses, devicetree: separate
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> Loading Environment from MMC... OK
> In:    serial at 5a060000
> Out:   serial at 5a060000
> Err:   serial at 5a060000
> Net:   eth0: ethernet at 5b040000
> Warning: ethernet at 5b050000 (eth1) using random MAC address - aa:a2:be:5b:81:4a
> , eth1: ethernet at 5b050000
> Hit any key to stop autoboot:  0
> 
> Signed-off-by: Oliver Graute <oliver.graute at kococonnector.com>
> ---
>  Changes for v4
>  -update atf fw version
>  -update seco fw version
>  -update scfw version
>  -move CONFIG_IMX_SMMU to imx8qm_dmsse20a1_defconfig
>  -move CONFIG_LOADADDR to imx8qm_dmsse20a1_defconfig
>  -move CONFIG_SYS_LOAD_ADDR to imx8qm_dmsse20a1_defconfig
>  -move CONFIG_SYS_MALLOC_LEN to imx8qm_dmsse20a1_defconfig
>  -move CONFIG_SYS_MMC_IMG_LOAD_PART to imx8qm_dmsse20a1_defconfig
>  -move CONFIG_FSL_USDHC to imx8qm_dmsse20a1_defconfig
>  -replaced CONFIG_SPL_MMC_SUPPORT with CONFIG_SPL_MMC
>  -replaced CONFIG_SPL_SERIAL_SUPPORT with CONFIG_SPL_SERIAL
>  -drop CONFIG_FEC_XCV_TYPE
> 
> Changes for v3
>  -Remove addr parameter from reset_cpu()
>  -moved some configs into defconfig
> 
> Changes for v2
>  -replaced bd_t with struct bd_info
>  -added missing DTS in MAINTAINERS
>  -replaced README with imx8qm-dmsse20-a1.rst
>  -move CMD_FUSE to Kconfig
>  -removed fdt_high
>  -added i2c support
>  -added rtc support
> 
>  arch/arm/dts/Makefile                         |   1 +
>  arch/arm/dts/imx8qm-dmsse20-a1.dts            | 407 ++++++++++++++++++
>  arch/arm/mach-imx/imx8/Kconfig                |   7 +
>  board/advantech/imx8qm_dmsse20_a1/Kconfig     |  17 +
>  board/advantech/imx8qm_dmsse20_a1/MAINTAINERS |   7 +
>  board/advantech/imx8qm_dmsse20_a1/Makefile    |   8 +
>  .../imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c     | 188 ++++++++
>  .../advantech/imx8qm_dmsse20_a1/imximage.cfg  |  21 +
>  board/advantech/imx8qm_dmsse20_a1/spl.c       | 224 ++++++++++
>  common/Kconfig                                |   2 +-
>  configs/imx8qm_dmsse20a1_defconfig            | 105 +++++
>  doc/board/advantech/imx8qm-dmsse20-a1.rst     |  59 +++
>  doc/board/advantech/index.rst                 |   1 +
>  include/configs/imx8qm_dmsse20.h              | 164 +++++++
>  14 files changed, 1210 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/imx8qm-dmsse20-a1.dts
>  create mode 100644 board/advantech/imx8qm_dmsse20_a1/Kconfig
>  create mode 100644 board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
>  create mode 100644 board/advantech/imx8qm_dmsse20_a1/Makefile
>  create mode 100644 board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
>  create mode 100644 board/advantech/imx8qm_dmsse20_a1/imximage.cfg
>  create mode 100644 board/advantech/imx8qm_dmsse20_a1/spl.c
>  create mode 100644 configs/imx8qm_dmsse20a1_defconfig
>  create mode 100644 doc/board/advantech/imx8qm-dmsse20-a1.rst
>  create mode 100644 include/configs/imx8qm_dmsse20.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index a7e0d9f6c0..50bc76289f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -920,6 +920,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
>         fsl-imx8qm-apalis.dtb \
>         fsl-imx8qm-mek.dtb \
>         imx8qm-cgtqmx8.dtb \
> +       imx8qm-dmsse20-a1.dtb \
>         imx8qm-rom7720-a1.dtb \
>         fsl-imx8qxp-ai_ml.dtb \
>         fsl-imx8qxp-colibri.dtb \
> diff --git a/arch/arm/dts/imx8qm-dmsse20-a1.dts b/arch/arm/dts/imx8qm-dmsse20-a1.dts
> new file mode 100644
> index 0000000000..81ef7fb2ce
> --- /dev/null
> +++ b/arch/arm/dts/imx8qm-dmsse20-a1.dts
> @@ -0,0 +1,407 @@
> +// SPDX-License-Identifier: GPL-2.0+

For device trees it is usually advisable to use the following license:

GPL-2.0-or-later OR MIT

Anyway, please use at least latest SPDX notation being GPL-2.0-or-later rather than GPL-2.0+.

> +/*
> + * Copyright 2017 NXP

That also seems bogus to me.

> + */
> +
> +/dts-v1/;
> +
> +/* First 128KB is for PSCI ATF. */
> +/memreserve/ 0x80000000 0x00020000;
> +
> +#include "fsl-imx8qm.dtsi"
> +
> +/ {
> +       model = "Advantech iMX8QM DMSSE20";
> +       compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
> +
> +       aliases {
> +          mmc0 = &usdhc1;
> +          mmc2 = &usdhc3;
> +       };
> +
> +       chosen {
> +               bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";

This stuff is completely downstream bogus.

> +               stdout-path = &lpuart0;
> +       };
> +
> +       regulators {

That grouping is also bogus.

> +               compatible = "simple-bus";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               reg_usb_otg1_vbus: regulator at 0 {
> +                       compatible = "regulator-fixed";
> +                       reg = <0>;

Using any such is also bogus (same with above @0 notation, of course).

> +                       regulator-name = "usb_otg1_vbus";
> +                       regulator-min-microvolt = <5000000>;
> +                       regulator-max-microvolt = <5000000>;
> +                       gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
> +                       enable-active-high;
> +               };
> +
> +               reg_usdhc2_vmmc: usdhc2_vmmc {
> +                       compatible = "regulator-fixed";
> +                       regulator-name = "sw-3p3-sd1";
> +                       regulator-min-microvolt = <3300000>;
> +                       regulator-max-microvolt = <3300000>;
> +                       gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
> +                       enable-active-high;
> +               };
> +
> +               busfreq {
> +                       status = "disabled";
> +               };
> +       };
> +};
> +
> +&iomuxc {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_hog_1>;
> +
> +       imx8qm-mek {
> +               pinctrl_hog_1: hoggrp-1 {

That notation vs. below without dash could also be cleaned up.

> +                       fsl,pins = <
> +                               SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03        0x06000048
> +                       >;
> +               };
> +
> +               pinctrl_fec1: fec1grp {
> +                       fsl,pins = <
> +                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD       0x000014a0
> +                               SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000020
> +                               SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000020
> +                               SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
> +                               SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC       0x00000060
> +                               SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x00000060
> +                               SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x00000060
> +                               SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2     0x00000060
> +                               SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3     0x00000060
> +                               SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC       0x00000060
> +                               SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
> +                               SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x00000060
> +                               SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x00000060
> +                               SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2     0x00000060
> +                               SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3     0x00000060
> +                       >;
> +               };
> +
> +               pinctrl_fec2: fec2grp {
> +                       fsl,pins = <
> +                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD       0x000014a0
> +                               SC_P_ENET1_MDC_CONN_ENET1_MDC                   0x06000020
> +                               SC_P_ENET1_MDIO_CONN_ENET1_MDIO                 0x06000020
> +                               SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
> +                               SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC       0x00000060
> +                               SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0     0x00000060
> +                               SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1     0x00000060
> +                               SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2     0x00000060
> +                               SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3     0x00000060
> +                               SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC       0x00000060
> +                               SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
> +                               SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0     0x00000060
> +                               SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1     0x00000060
> +                               SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2     0x00000060
> +                               SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3     0x00000060
> +                       >;
> +               };
> +
> +               pinctrl_lpi2c1: lpi2c1grp {
> +                       fsl,pins = <
> +                               SC_P_GPT0_CLK_DMA_I2C1_SCL              0xc600004c
> +                               SC_P_GPT0_CAPTURE_DMA_I2C1_SDA          0xc600004c
> +                       >;
> +               };
> +
> +               pinctrl_lpi2c2: lpi2c2grp {
> +                       fsl,pins = <
> +                               SC_P_GPT1_CLK_DMA_I2C2_SCL              0xc600004c
> +                               SC_P_GPT1_CAPTURE_DMA_I2C2_SDA          0xc600004c
> +                       >;
> +               };
> +
> +               pinctrl_lpuart0: lpuart0grp {
> +                       fsl,pins = <
> +                               SC_P_UART0_RX_DMA_UART0_RX              0x06000020
> +                               SC_P_UART0_TX_DMA_UART0_TX              0x06000020
> +                       >;
> +               };
> +
> +               pinctrl_rtc_mc_8803: rtc_mc_8803_grp{

Underscores in node names. Ugh!

> +                       fsl,pins = <
> +                               SC_P_SIM0_POWER_EN_DMA_I2C3_SDA         0xc600004c
> +                               SC_P_SIM0_PD_DMA_I2C3_SCL               0xc600004c
> +                       >;
> +               };
> +
> +               pinctrl_usdhc1: usdhc1grp {
> +                       fsl,pins = <
> +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000041
> +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000021
> +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000021
> +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000021
> +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000021
> +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000021
> +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000021
> +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
> +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
> +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
> +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000041
> +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {

I believe this speed denomination is the very only place dashes would be used. See e.g. here

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/freescale/imx8mp-evk.dts#n578

> +                       fsl,pins = <
> +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000040
> +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000020
> +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000020
> +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000020
> +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000020
> +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000020
> +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000020
> +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
> +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
> +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
> +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
> +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000020
> +                       >;
> +               };
> +
> +               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +                       fsl,pins = <
> +                               SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000040
> +                               SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000020
> +                               SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000020
> +                               SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000020
> +                               SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000020
> +                               SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000020
> +                               SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000020
> +                               SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000020
> +                               SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000020
> +                               SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000020
> +                               SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x06000040
> +                               SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000020
> +                       >;
> +               };
> +
> +               pinctrl_usdhc2_gpio: usdhc2grpgpio {
> +                       fsl,pins = <
> +                               SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07     0x00000020
> +                               SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08     0x00000020
> +                       >;
> +               };
> +
> +               pinctrl_usdhc3_gpio: usdhc3grpgpio {
> +                       fsl,pins = <
> +                               SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000021
> +                               SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc2: usdhc2grp {
> +                       fsl,pins = <
> +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
> +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
> +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
> +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
> +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
> +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
> +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +                       fsl,pins = <
> +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000040
> +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000020
> +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000020
> +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000020
> +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000020
> +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000020
> +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
> +                       >;
> +               };
> +
> +               pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +                       fsl,pins = <
> +                               SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000040
> +                               SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000020
> +                               SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000020
> +                               SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000020
> +                               SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000020
> +                               SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000020
> +                               SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
> +                       >;
> +               };
> +
> +               pinctrl_usdhc3: usdhc3grp {
> +                       fsl,pins = <
> +                               SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000041
> +                               SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000021
> +                               SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000021
> +                               SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000021
> +                               SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000021
> +                               SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000021
> +                               SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
> +                       >;
> +               };
> +
> +               pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> +                       fsl,pins = <
> +                               SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
> +                               SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
> +                               SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
> +                               SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
> +                               SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
> +                               SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
> +                               SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
> +                       >;
> +               };
> +
> +               pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> +                       fsl,pins = <
> +                               SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
> +                               SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
> +                               SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
> +                               SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
> +                               SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
> +                               SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
> +                               SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
> +                       >;
> +               };
> +       };
> +};
> +
> +&gpio2 {
> +       status = "okay";
> +};
> +
> +&gpio4 {
> +       status = "okay";
> +};
> +
> +&gpio5 {
> +       status = "okay";
> +};
> +
> +&usdhc1 {
> +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +       pinctrl-0 = <&pinctrl_usdhc1>;
> +       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> +       bus-width = <8>;
> +       non-removable;
> +       status = "okay";
> +};
> +
> +&usdhc2 {
> +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> +       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> +       bus-width = <4>;
> +       cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
> +       wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
> +       vmmc-supply = <&reg_usdhc2_vmmc>;

I would sort those alphabetically.

> +       status = "okay";
> +};
> +
> +&usdhc3 {
> +       pinctrl-names = "default","state_100mhz", "state_200mhz";
> +       pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
> +       pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
> +       pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
> +       bus-width = <4>;
> +       cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
> +       wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
> +       no-1-8-v;

Ditto.

> +       status = "okay";
> +};
> +
> +&fec1 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_fec1>;
> +       phy-mode = "rgmii-id";
> +       phy-handle = <&ethphy0>;
> +       fsl,ar8031-phy-fixup;
> +       fsl,magic-packet;

D.

> +       status = "okay";
> +
> +       mdio {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               ethphy0: ethernet-phy at 4 {
> +                       compatible = "ethernet-phy-ieee802.3-c22";
> +                       reg = <4>;
> +               };
> +       };
> +};
> +
> +&fec2 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_fec2>;
> +       phy-mode = "rgmii-id";
> +       phy-handle = <&ethphy1>;
> +       fsl,ar8031-phy-fixup;
> +       fsl,magic-packet;
> +       status = "okay";
> +       fsl,mii-exclusive;

That actually is just downstream only NXP bogus.

> +
> +       mdio {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               ethphy1: ethernet-phy at 4 {
> +                       compatible = "ethernet-phy-ieee802.3-c22";
> +                       reg = <4>;
> +               };
> +       };
> +};
> +
> +&i2c1 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       clock-frequency = <100000>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_lpi2c1>;
> +       status = "okay";
> +};
> +
> +&i2c2 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       clock-frequency = <100000>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_lpi2c2>;
> +       status = "okay";
> +};
> +
> +&i2c3 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       clock-frequency = <100000>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_rtc_mc_8803>;
> +       status = "okay";
> +
> +       rv8803 at 32 {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               compatible = "microcrystal,rv8803";
> +               reg = <0x32>;
> +       };
> +
> +       24c02 at 50 {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               compatible = "atmel,24c04";
> +               reg = <0x50>;
> +       };
> +};
> +
> +&lpuart0 { /* console */
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_lpuart0>;
> +       status = "okay";
> +};
> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
> index 5e1b20a422..bcb60b1e90 100644
> --- a/arch/arm/mach-imx/imx8/Kconfig
> +++ b/arch/arm/mach-imx/imx8/Kconfig
> @@ -84,6 +84,12 @@ config TARGET_IMX8QM_ROM7720_A1
>         select SUPPORT_SPL
>         select IMX8QM
>  
> +config TARGET_IMX8QM_DMSSE20_A1
> +       bool "Support i.MX8QM DMS-SE20-A1 board"
> +       select BOARD_LATE_INIT
> +       select SUPPORT_SPL
> +       select IMX8QM
> +
>  config TARGET_IMX8QXP_MEK
>         bool "Support i.MX8QXP MEK board"
>         select BOARD_LATE_INIT
> @@ -97,6 +103,7 @@ endchoice
>  source "board/freescale/imx8qm_mek/Kconfig"
>  source "board/freescale/imx8qxp_mek/Kconfig"
>  source "board/congatec/cgtqmx8/Kconfig"
> +source "board/advantech/imx8qm_dmsse20_a1/Kconfig"
>  source "board/advantech/imx8qm_rom7720_a1/Kconfig"
>  source "board/toradex/apalis-imx8/Kconfig"
>  source "board/toradex/colibri-imx8x/Kconfig"
> diff --git a/board/advantech/imx8qm_dmsse20_a1/Kconfig b/board/advantech/imx8qm_dmsse20_a1/Kconfig
> new file mode 100644
> index 0000000000..f491462ea0
> --- /dev/null
> +++ b/board/advantech/imx8qm_dmsse20_a1/Kconfig
> @@ -0,0 +1,17 @@
> +if TARGET_IMX8QM_DMSSE20_A1
> +
> +config SYS_BOARD
> +       default "imx8qm_dmsse20_a1"
> +
> +config SYS_VENDOR
> +       default "advantech"
> +
> +config SYS_CONFIG_NAME
> +       default "imx8qm_dmsse20"
> +
> +config IMX_CONFIG
> +       default "board/advantech/imx8qm_dmsse20_a1/imximage.cfg"
> +
> +source "board/freescale/common/Kconfig"
> +
> +endif
> diff --git a/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
> new file mode 100644
> index 0000000000..8292c6ba71
> --- /dev/null
> +++ b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
> @@ -0,0 +1,7 @@
> +i.MX8QM ROM DMSSE20 a1 BOARD
> +M:     Oliver Graute <oliver.graute at kococonnector.com>
> +S:     Maintained
> +F:     board/advantech/imx8qm_dmsse20_a1/
> +F:     arch/arm/dts/imx8qm-dmsse20-a1.dtb
> +F:     include/configs/imx8qm_dmsse20.h
> +F:     configs/imx8qm_dmsse20a1_defconfig
> diff --git a/board/advantech/imx8qm_dmsse20_a1/Makefile b/board/advantech/imx8qm_dmsse20_a1/Makefile
> new file mode 100644
> index 0000000000..262ffcd683
> --- /dev/null
> +++ b/board/advantech/imx8qm_dmsse20_a1/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Copyright 2017 NXP

D.

> +#
> +# SPDX-License-Identifier:     GPL-2.0+

D.

> +#
> +
> +obj-y += imx8qm_dmsse20_a1.o
> +obj-$(CONFIG_SPL_BUILD) += spl.o
> diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
> b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
> new file mode 100644
> index 0000000000..c3bc26f80d
> --- /dev/null
> +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
> @@ -0,0 +1,188 @@
> +// SPDX-License-Identifier: GPL-2.0+

D.

> +/*
> + * Copyright 2017-2018 NXP
> + * Copyright (C) 2020 Oliver Graute <oliver.graute at kococonnector.com>

How the time flies.

> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <linux/libfdt.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sci/sci.h>
> +#include <asm/arch/imx8-pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/sys_proto.h>
> +/* #include <power-domain.h> */
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL  ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
> +                       (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +                       (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +                       (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +static iomux_cfg_t uart0_pads[] = {
> +       SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +       SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> +       imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
> +}
> +
> +int board_early_init_f(void)
> +{
> +       sc_pm_clock_rate_t rate = SC_80MHZ;
> +       int ret;
> +
> +       /* Set UART0 clock root to 80 MHz */
> +       ret = sc_pm_setup_uart(SC_R_UART_0, rate);
> +       if (ret)
> +               return ret;
> +
> +       setup_iomux_uart();
> +
> +       /* This is needed to because Kernel do not Power Up DC_0 */
> +       sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON);
> +       sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
> +
> +       return 0;
> +}
> +
> +#if IS_ENABLED(CONFIG_FEC_MXC)
> +#include <miiphy.h>
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> +       if (phydev->drv->config)
> +               phydev->drv->config(phydev);
> +
> +       return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_MXC_GPIO
> +
> +#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
> +#define MIPI_ENABLE IMX_GPIO_NR(1, 7)
> +
> +#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
> +#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
> +#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
> +
> +static void board_gpio_init(void)
> +{
> +       /* Enable BB 3V3 */
> +       gpio_request(BB_GPIO_3V3_1, "bb_3v3_1");
> +       gpio_direction_output(BB_GPIO_3V3_1, 1);
> +       gpio_request(BB_GPIO_3V3_2, "bb_3v3_2");
> +       gpio_direction_output(BB_GPIO_3V3_2, 1);
> +       gpio_request(BB_GPIO_3V3_3, "bb_3v3_3");
> +       gpio_direction_output(BB_GPIO_3V3_3, 1);
> +
> +       /* enable LVDS SAS boards */
> +       gpio_request(LVDS_ENABLE, "lvds_enable");
> +       gpio_direction_output(LVDS_ENABLE, 1);
> +
> +       /* enable MIPI SAS boards */
> +       gpio_request(MIPI_ENABLE, "mipi_enable");
> +       gpio_direction_output(MIPI_ENABLE, 1);
> +}
> +#endif
> +
> +int checkboard(void)
> +{
> +       puts("Board: DMS-SE20A1 8GB\n");
> +       build_info();
> +       print_bootinfo();
> +
> +       return 0;
> +}
> +
> +int board_init(void)
> +{
> +       if (IS_ENABLED(CONFIG_XEN))
> +               return 0;
> +
> +#ifdef CONFIG_MXC_GPIO
> +       board_gpio_init();
> +#endif
> +
> +       return 0;
> +}
> +
> +void board_quiesce_devices(void)
> +{
> +       if (IS_ENABLED(CONFIG_XEN)) {
> +               /* Clear magic number to let xen know uboot is over */
> +               writel(0x0, (void __iomem *)0x80000000);
> +               return;
> +       }
> +}
> +
> +void detail_board_ddr_info(void)
> +{
> +       puts("\nDDR    ");
> +}
> +
> +/*
> + * Board specific reset that is system reset.
> + */
> +void reset_cpu(void)
> +{
> +       puts("SCI reboot request");
> +
> +       while (1)
> +               putc('.');
> +}
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, struct bd_info *bd)
> +{
> +       return 0;
> +}
> +#endif
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> +       /* Use EMMC */
> +       if (IS_ENABLED(CONFIG_XEN))
> +               return 0;
> +
> +       return devno;
> +}
> +
> +int mmc_map_to_kernel_blk(int dev_no)
> +{
> +       /* Use EMMC */
> +       if (IS_ENABLED(CONFIG_XEN))
> +               return 0;
> +
> +       return dev_no;
> +}
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +       env_set("board_name", "DMS-SE20A1");
> +       env_set("board_rev", "iMX8QM");
> +#endif
> +
> +       env_set("sec_boot", "no");
> +#ifdef CONFIG_AHAB_BOOT
> +       env_set("sec_boot", "yes");
> +#endif
> +
> +       return 0;
> +}
> diff --git a/board/advantech/imx8qm_dmsse20_a1/imximage.cfg b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg
> new file mode 100644
> index 0000000000..e324c7ca37
> --- /dev/null
> +++ b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier:    GPL-2.0+ */

D.

> +/*
> + * Copyright 2018 NXP

D.

> + */
> +
> +#define __ASSEMBLY__
> +
> +/* Boot from SD, sector size 0x400 */
> +BOOT_FROM SD 0x400
> +/* SoC type IMX8QM */
> +SOC_TYPE IMX8QM
> +/* Append seco container image */
> +APPEND mx8qm-ahab-container.img
> +/* Create the 2nd container */
> +CONTAINER
> +/* Add scfw image with exec attribute */
> +IMAGE SCU mx8qm-val-scfw-tcm.bin
> +/* Add ATF image with exec attribute */
> +IMAGE A35 bl31.bin 0x80000000
> +/* Add U-Boot image with load attribute */
> +DATA A35 u-boot-dtb.bin 0x80020000
> diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c
> new file mode 100644
> index 0000000000..06bb049c3a
> --- /dev/null
> +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c
> @@ -0,0 +1,224 @@
> +// SPDX-License-Identifier: GPL-2.0+

D.

> +/*
> + * Copyright 2017-2018 NXP

D.

> + */
> +#include <common.h>
> +#include <dm.h>
> +#include <spl.h>
> +#include <fsl_esdhc.h>
> +
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sci/sci.h>
> +#include <asm/arch/imx8-pins.h>
> +#include <asm/arch/iomux.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +               (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +               (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +               (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define ESDHC_CLK_PAD_CTRL     ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
> +               (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +               (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +               (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define ENET_INPUT_PAD_CTRL    ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
> +               (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +               (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
> +               (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define ENET_NORMAL_PAD_CTRL   ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +               (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +               (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
> +               (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define FSPI_PAD_CTRL  ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +               (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +               (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +               (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define GPIO_PAD_CTRL  ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
> +               (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +               (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +               (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define I2C_PAD_CTRL   ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
> +               (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +               (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
> +               (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +
> +#define UART_PAD_CTRL  ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
> +               (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
> +               (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
> +               (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
> +#ifdef CONFIG_FSL_ESDHC_IMX
> +
> +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
> +
> +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
> +       {USDHC1_BASE_ADDR, 0, 8},
> +       {USDHC3_BASE_ADDR, 0, 4},
> +};
> +
> +static iomux_cfg_t emmc0[] = {
> +       SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
> +       SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +};
> +
> +static iomux_cfg_t usdhc2_sd[] = {
> +       SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
> +       SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_USDHC2_WP   | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +       SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +};
> +
> +void init_clk_usdhc(u32 index);
> +int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg);
> +int arch_cpu_init(void);
> +int board_early_init_f(void);
> +int timer_init(void);
> +void board_init_r(gd_t *id, ulong dest_addr);
> +
> +int board_mmc_init(struct bd_info *bis)
> +{
> +       int i, ret;
> +
> +       /*
> +        * According to the board_mmc_init() the following map is done:
> +        * (U-Boot device node)    (Physical Port)
> +        * mmc0                    USDHC1
> +        * mmc1                    USDHC2
> +        * mmc2                    USDHC3
> +        */
> +       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> +               switch (i) {
> +               case 0:
> +                       ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
> +                       if (ret != SC_ERR_NONE)
> +                               return ret;
> +
> +                       imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
> +                       init_clk_usdhc(0);
> +                       usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> +                       break;
> +               case 1:
> +                       ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
> +                       if (ret != SC_ERR_NONE)
> +                               return ret;
> +                       ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
> +                       if (ret != SC_ERR_NONE)
> +                               return ret;
> +
> +                       imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
> +                       init_clk_usdhc(2);
> +                       usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> +                       gpio_request(USDHC2_CD_GPIO, "sd2_cd");
> +                       gpio_direction_input(USDHC2_CD_GPIO);
> +                       break;
> +               default:
> +                       printf("Warning: you configured more USDHC controllers"
> +                               "(%d) than supported by the board\n", i + 1);
> +                       return 0;
> +               }
> +               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> +               if (ret) {
> +                       printf("Warning: failed to initialize mmc dev %d\n", i);
> +                       return ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> +       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +       int ret = 0;
> +
> +       switch (cfg->esdhc_base) {
> +       case USDHC1_BASE_ADDR:
> +               ret = 1;
> +               break;
> +       case USDHC2_BASE_ADDR:
> +               ret = !gpio_get_value(USDHC1_CD_GPIO);
> +               break;
> +       case USDHC3_BASE_ADDR:
> +               ret = !gpio_get_value(USDHC2_CD_GPIO);
> +               break;
> +       }
> +
> +       return ret;
> +}
> +
> +#endif /* CONFIG_FSL_ESDHC_IMX */
> +
> +void spl_board_init(void)
> +{
> +#if defined(CONFIG_SPL_SPI_SUPPORT)
> +       if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
> +               if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON))
> +                       puts("Warning: failed to initialize FSPI0\n");
> +       }
> +#endif
> +
> +       puts("Normal Boot\n");
> +}
> +
> +void spl_board_prepare_for_boot(void)
> +{
> +#if defined(CONFIG_SPL_SPI_SUPPORT)
> +       if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
> +               if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF))
> +                       puts("Warning: failed to turn off FSPI0\n");
> +       }
> +#endif
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +       /* Just empty function now - can't decide what to choose */
> +       debug("%s: %s\n", __func__, name);
> +
> +       return 0;
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> +       /* Clear global data */
> +       memset((void *)gd, 0, sizeof(gd_t));
> +
> +       arch_cpu_init();
> +
> +       board_early_init_f();
> +
> +       timer_init();
> +
> +       preloader_console_init();
> +
> +       /* Clear the BSS. */
> +       memset(__bss_start, 0, __bss_end - __bss_start);
> +
> +       board_init_r(NULL, 0);
> +}
> diff --git a/common/Kconfig b/common/Kconfig
> index a96842a5c1..894733a26e 100644
> --- a/common/Kconfig
> +++ b/common/Kconfig
> @@ -528,7 +528,7 @@ config BOARD_TYPES
>  
>  config DISPLAY_CPUINFO
>         bool "Display information about the CPU during start up"
> -       default y if ARC|| ARM || NIOS2 || X86 || XTENSA || M68K
> +       default y if ARC || ARM || NIOS2 || X86 || XTENSA || M68K

That unrelated change would probably mandate a separate commit.

>         help
>           Display information about the CPU that U-Boot is running on
>           when U-Boot starts up. The function print_cpuinfo() is called
> diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig
> new file mode 100644
> index 0000000000..569401cf56
> --- /dev/null
> +++ b/configs/imx8qm_dmsse20a1_defconfig
> @@ -0,0 +1,105 @@
> +CONFIG_ARM=y
> +CONFIG_SPL_SYS_ICACHE_OFF=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
> +CONFIG_ARCH_IMX8=y
> +CONFIG_SYS_TEXT_BASE=0x80020000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_LEN=0x2800000
> +CONFIG_SYS_MALLOC_F_LEN=0x4000
> +CONFIG_SYS_MMC_IMG_LOAD_PART=0
> +CONFIG_TARGET_IMX8QM_DMSSE20_A1=y
> +CONFIG_SPL_MMC=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SPL_DRIVERS_MISC=y
> +CONFIG_ENV_OFFSET=0x80000
> +CONFIG_SPL=y
> +CONFIG_SYS_LOAD_ADDR=0x80280000
> +CONFIG_FIT=y
> +CONFIG_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> +CONFIG_OF_CONTROL=y
> +CONFIG_CI_UDC=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_LOG=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +CONFIG_SPL_POWER_DOMAIN=y
> +CONFIG_SPL_WATCHDOG_SUPPORT=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_IMX_BOOTAUX=y
> +CONFIG_FS_FAT=y
> +CONFIG_FS_EXT4=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_DM_MMC=y
> +CONFIG_MMC_IO_VOLTAGE=y
> +CONFIG_MMC_UHS_SUPPORT=y
> +CONFIG_MMC_HS400_SUPPORT=y
> +CONFIG_MMC_BROKEN_CD=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx8qm-dmsse20-a1"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_CLK=y
> +CONFIG_CLK_IMX8=y
> +CONFIG_CPU=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_FSL_ESDHC_IMX=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ADDR_ENABLE=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_DM_ETH=y
> +# CONFIG_EFI_LOADER is not set
> +CONFIG_FEC_MXC_SHARE_MDIO=y
> +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
> +CONFIG_FEC_MXC=y
> +CONFIG_FEC1_ENET_DEV=0
> +CONFIG_ETHPRIME="eth0"
> +CONFIG_FEC1_MXC_PHYADDR=0x4
> +CONFIG_FEC2_ENET_DEV=1
> +CONFIG_ETHPRIME1="eth1"
> +CONFIG_FEC2_MXC_PHYADDR=0x4
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_IMX8_POWER_DOMAIN=y
> +CONFIG_IMX_SMMU=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_SPL_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_SPL_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_FSL_LPUART=y
> +CONFIG_MISC=y
> +CONFIG_SMC_FUSE=y
> +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
> +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_SPL_TINY_MEMSET=y
> +CONFIG_AHAB_BOOT=y
> +CONFIG_SYS_I2C_IMX_LPI2C=y
> +CONFIG_DM_RTC=y
> +CONFIG_RTC_RV8803=y
> +CONFIG_CMD_DATE=y
> +# CONFIG_CMD_DEKBLOB is not set
> diff --git a/doc/board/advantech/imx8qm-dmsse20-a1.rst b/doc/board/advantech/imx8qm-dmsse20-a1.rst
> new file mode 100644
> index 0000000000..bb116fa374
> --- /dev/null
> +++ b/doc/board/advantech/imx8qm-dmsse20-a1.rst
> @@ -0,0 +1,59 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +NXP i.MX8QM DMSSE20-a1 board
> +============================
> +
> +Quick Start
> +-----------
> +
> +- Build the ARM Trusted firmware binary
> +- Get scfw_tcm.bin and ahab-container.img
> +- Get imx-mkimage
> +- Build U-Boot
> +- Flash the binary into the SD card
> +- Boot
> +
> +Get and Build the ARM Trusted Firmware
> +--------------------------------------
> +
> +.. code-block:: bash
> +
> +     $ git clone https://source.codeaurora.org/external/imx/imx-atf
> +     $ cd imx-atf/
> +     $ git checkout lf-5.10.72-2.2.0 -b lf-5.10.72-2.2.0
> +     $ make PLAT=imx8qm bl31
> +     $ cp build/imx8qm/release/bl31.bin $(builddir)
> +
> +Get scfw_tcm.bin and ahab-container.img
> +---------------------------------------
> +
> +.. code-block:: bash
> +
> +     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.11.0.bin
> +     $ chmod +x imx-sc-firmware-1.11.0.bin
> +     $ ./imx-sc-firmware-1.11.0.bin
> +     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.8.5.bin
> +     $ chmod +x imx-seco-3.8.5.bin
> +     $ ./imx-seco-3.8.5.bin
> +
> +Or use this to avoid running random scripts from the internet,
> +but note that you must agree to the license the script displays:
> +
> +.. code-block:: bash
> +
> +     $ dd if=imx-sc-firmware-1.11.0.bin of=imx-sc-firmware-1.11.0.tar.bz2 bs=42757 skip=1
> +     $ tar -xf imx-sc-firmware-1.11.0.tar.bz2
> +     $ cp imx-sc-firmware-1.11.0/mx8qm-val-scfw-tcm.bin $(builddir)
> +     $ dd if=imx-seco-3.8.5.bin of=imx-seco-3.8.5.tar.bz2 bs=43978 skip=1
> +     $ tar -xf imx-seco-3.8.5.tar.bz2
> +     $ cp imx-seco-3.8.5/firmware/seco/mx8qmb0-ahab-container.img $(builddir)
> +
> +Build U-Boot
> +------------
> +.. code-block:: bash
> +
> +     $ export ATF_LOAD_ADDR=0x80000000
> +     $ export BL33_LOAD_ADDR=0x80020000
> +     $ make imx8qm_dmsse20a1_defconfig
> +     $ make u-boot.bin
> +     $ make flash.bin
> diff --git a/doc/board/advantech/index.rst b/doc/board/advantech/index.rst
> index e9b198c5c3..125b98c1f7 100644
> --- a/doc/board/advantech/index.rst
> +++ b/doc/board/advantech/index.rst
> @@ -7,3 +7,4 @@ Advantech
>     :maxdepth: 2
>  
>     imx8qm-rom7720-a1.rst
> +   imx8qm-dmsse20-a1.rst
> diff --git a/include/configs/imx8qm_dmsse20.h b/include/configs/imx8qm_dmsse20.h
> new file mode 100644
> index 0000000000..3050f79fa7
> --- /dev/null
> +++ b/include/configs/imx8qm_dmsse20.h
> @@ -0,0 +1,164 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2017-2019 NXP
> + */
> +
> +#ifndef __IMX8QM_DMSSE20_H
> +#define __IMX8QM_DMSSE20_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_SPL_MAX_SIZE            (124 * 1024)
> +#define CONFIG_SPL_BSS_START_ADDR      0x00128000
> +#define CONFIG_SPL_BSS_MAX_SIZE        0x1000  /* 4 KB */
> +
> +#define CONFIG_NR_DRAM_BANKS           4
> +
> +/* Flat Device Tree Definitions */
> +#define CONFIG_OF_BOARD_SETUP
> +
> +#undef CONFIG_BOOTM_NETBSD
> +
> +#define CONFIG_SYS_FSL_ESDHC_ADDR      0
> +#define USDHC1_BASE_ADDR               0x5B010000
> +#define USDHC2_BASE_ADDR               0x5B020000
> +#define USDHC3_BASE_ADDR               0x5B030000
> +
> +#define CONFIG_SUPPORT_EMMC_BOOT       /* eMMC specific */
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +
> +#define FEC_QUIRK_ENET_MAC
> +
> +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
> +
> +#define IMX_FEC_BASE                   0x5B040000
> +/* FEC1 */
> +#define IMX_FEC1_BASE                  0x5B040000
> +/* FEC2 */
> +#define IMX_FEC2_BASE                  0x5B050000
> +
> +#ifdef CONFIG_NAND_BOOT
> +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
> +#else
> +#define MFG_NAND_PARTITION ""
> +#endif
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS              \
> +       "script=boot.scr\0" \
> +       "image=Image\0" \
> +       "panel=NULL\0" \
> +       "console=ttyLP0\0" \
> +       "earlycon=lpuart32,0x5a060000\0" \
> +       "fdt_addr=0x83000000\0"                 \
> +       "boot_fdt=try\0" \
> +       "fdt_file=imx8qm-dmsse20-a1.dtb\0" \
> +       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
> +       "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> +       "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
> +       "mmcautodetect=yes\0" \
> +       "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate}
> root=${mmcroot}\0 " \
> +       "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> +       "bootscript=echo Running bootscript from mmc ...; " \
> +               "source\0" \
> +       "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> +       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> +       "mmcboot=echo Booting from mmc ...; " \
> +               "run mmcargs; " \
> +               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +                       "if run loadfdt; then " \
> +                               "booti ${loadaddr} - ${fdt_addr}; " \
> +                       "else " \
> +                               "echo WARN: Cannot load the DT; " \
> +                       "fi; " \
> +               "else " \
> +                       "echo wait for boot; " \
> +               "fi;\0" \
> +       "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \
> +               "root=/dev/nfs " \
> +               "ip=dhcp mac=${ethaddr} nfsroot=${serverip}:${nfsroot},v3,tcp rw\0" \
> +       "netboot=echo Booting from net ...; " \
> +               "run netargs;  " \
> +               "if test ${ip_dyn} = yes; then " \
> +                       "setenv get_cmd dhcp; " \
> +               "else " \
> +                       "setenv get_cmd tftp; " \
> +               "fi; " \
> +               "${get_cmd} ${loadaddr} ${image}; " \
> +               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> +                               "booti ${loadaddr} - ${fdt_addr}; " \
> +                       "else " \
> +                               "echo WARN: Cannot load the DT; " \
> +                       "fi; " \
> +               "else " \
> +                       "booti; " \
> +               "fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> +          "mmc dev ${mmcdev}; if mmc rescan; then " \
> +                  "if run loadbootscript; then " \
> +                          "run bootscript; " \
> +                  "else " \
> +                          "if run loadimage; then " \
> +                                  "run mmcboot; " \
> +                          "else run netboot; " \
> +                          "fi; " \
> +                  "fi; " \
> +          "else booti ${loadaddr} - ${fdt_addr}; fi"
> +
> +/* Link Definitions */
> +
> +#define CONFIG_SYS_INIT_SP_ADDR                0x80200000
> +
> +/* Default environment is in SD */
> +
> +#ifdef CONFIG_QSPI_BOOT
> +#define CONFIG_ENV_SECT_SIZE   (128 * 1024)
> +#define CONFIG_ENV_SPI_BUS     CONFIG_SF_DEFAULT_BUS
> +#define CONFIG_ENV_SPI_CS      CONFIG_SF_DEFAULT_CS
> +#define CONFIG_ENV_SPI_MODE    CONFIG_SF_DEFAULT_MODE
> +#define CONFIG_ENV_SPI_MAX_HZ  CONFIG_SF_DEFAULT_SPEED
> +#else
> +#define CONFIG_SYS_MMC_ENV_PART                0       /* user area */
> +#endif
> +
> +#define CONFIG_SYS_MMC_ENV_DEV         2   /* USDHC3 */
> +#define CONFIG_SYS_FSL_USDHC_NUM       2
> +
> +#define CONFIG_SYS_SDRAM_BASE          0x080000000
> +#define PHYS_SDRAM_1                   0x080000000
> +#define PHYS_SDRAM_2                   0x880000000
> +#define PHYS_SDRAM_1_SIZE              0x080000000     /* 2 GB */
> +#define PHYS_SDRAM_2_SIZE              0x180000000     /* 6 GB */
> +
> +#define CONFIG_SYS_MEMTEST_START       0xA0000000
> +#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2))
> +
> +/* Serial */
> +#define CONFIG_BAUDRATE                        115200
> +
> +/* Generic Timer Definitions */
> +#define COUNTER_FREQUENCY              8000000 /* 8MHz */
> +
> +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
> +#ifdef CONFIG_FSL_FSPI
> +#define CONFIG_SF_DEFAULT_BUS          0
> +#define CONFIG_SF_DEFAULT_CS           0
> +#define CONFIG_SF_DEFAULT_SPEED                40000000
> +#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
> +#define FSL_FSPI_FLASH_SIZE            SZ_64M
> +#define FSL_FSPI_FLASH_NUM             1
> +#define FSPI0_BASE_ADDR                        0x5d120000
> +#define FSPI0_AMBA_BASE                        0
> +#define CONFIG_SYS_FSL_FSPI_AHB
> +#endif
> +
> +/* #define CONFIG_OF_SYSTEM_SETUP */
> +
> +#endif /* __IMX8QM_DMSSE20_H */

Otherwise looks great. Keep up the good work!

Cheers

Marcel


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