[PATCH] imx8mm: Sync device tree with linux-next 20220711
ZHIZHIKIN Andrey
andrey.zhizhikin at leica-geosystems.com
Fri Jul 15 22:11:46 CEST 2022
Hello Fabio,
> -----Original Message-----
> From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Fabio Estevam
> Sent: Friday, July 15, 2022 6:57 PM
> To: sbabic at denx.de
> Cc: andrey.zhizhikin at leica-geosystems.com; u-boot at lists.denx.de; uboot-
> imx at nxp.com; gaurav.jain at nxp.com; Fabio Estevam <festevam at denx.de>
> Subject: [PATCH] imx8mm: Sync device tree with linux-next 20220711
>
> From: Fabio Estevam <festevam at denx.de>
>
> Sync imx8mm.dtsi device tree with linux-next 20220711.
>
> The main motivation for doing this sync is the sha256 regression
> reported by Andrey Zhizhikin [1].
>
First of, thanks a lot for the quick response and the patch!
While this solves the SHA computations for i.MX8MM, I just tested and
confirmed that the same issue persists on i.MX8MN and i.MX8MP as well...
It looks like the same is required for all other derivatives of i.MX8M
family which have CAAM enables by default...
> The linux-next kernel has the following commit, which disables
> the job ring 0 and fixes the problem:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-
> next.git/commit/?h=next-20220715&id=dc9c1ceb555ff661e6fc1081434600771f29657c
>
> [1] https://lore.kernel.org/u-
> boot/AM6PR06MB46912207D9460CD9924F35DAA68B9 at AM6PR06MB4691.eurprd06.prod.outlook.c
> om/T/#t
>
> Signed-off-by: Fabio Estevam <festevam at denx.de>
> ---
> arch/arm/dts/imx8mm.dtsi | 653 ++++++++++++++++-------
> include/dt-bindings/power/imx8mm-power.h | 9 +
> 2 files changed, 456 insertions(+), 206 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
> index 724f6ddbf397..afb90f59c83c 100644
> --- a/arch/arm/dts/imx8mm.dtsi
> +++ b/arch/arm/dts/imx8mm.dtsi
> @@ -4,11 +4,11 @@
> */
>
> #include <dt-bindings/clock/imx8mm-clock.h>
> -#include <dt-bindings/power/imx8mm-power.h>
> -#include <dt-bindings/reset/imx8mq-reset.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/imx8mm-power.h>
> +#include <dt-bindings/reset/imx8mq-reset.h>
> #include <dt-bindings/thermal/thermal.h>
>
> #include "imx8mm-pinfunc.h"
> @@ -65,6 +65,12 @@
> clock-latency = <61036>; /* two CLK32 periods */
> clocks = <&clk IMX8MM_CLK_ARM>;
> enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> next-level-cache = <&A53_L2>;
> operating-points-v2 = <&a53_opp_table>;
> nvmem-cells = <&cpu_speed_grade>;
> @@ -80,6 +86,12 @@
> clock-latency = <61036>; /* two CLK32 periods */
> clocks = <&clk IMX8MM_CLK_ARM>;
> enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> next-level-cache = <&A53_L2>;
> operating-points-v2 = <&a53_opp_table>;
> cpu-idle-states = <&cpu_pd_wait>;
> @@ -93,6 +105,12 @@
> clock-latency = <61036>; /* two CLK32 periods */
> clocks = <&clk IMX8MM_CLK_ARM>;
> enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> next-level-cache = <&A53_L2>;
> operating-points-v2 = <&a53_opp_table>;
> cpu-idle-states = <&cpu_pd_wait>;
> @@ -106,6 +124,12 @@
> clock-latency = <61036>; /* two CLK32 periods */
> clocks = <&clk IMX8MM_CLK_ARM>;
> enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> next-level-cache = <&A53_L2>;
> operating-points-v2 = <&a53_opp_table>;
> cpu-idle-states = <&cpu_pd_wait>;
> @@ -114,6 +138,10 @@
>
> A53_L2: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> };
> };
>
> @@ -184,7 +212,7 @@
> clk_ext4: clock-ext4 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> - clock-frequency= <133000000>;
> + clock-frequency = <133000000>;
> clock-output-names = "clk_ext4";
> };
>
> @@ -194,10 +222,9 @@
> };
>
> pmu {
> - compatible = "arm,armv8-pmuv3";
> + compatible = "arm,cortex-a53-pmu";
> interrupts = <GIC_PPI 7
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> - interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
> };
>
> timer {
> @@ -260,11 +287,14 @@
> clock-names = "main_clk";
> };
>
> - soc at 0 {
> - compatible = "simple-bus";
> + soc: soc at 0 {
> + compatible = "fsl,imx8mm-soc", "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x0 0x0 0x0 0x3e000000>;
> + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
> + nvmem-cells = <&imx8mm_uid>;
> + nvmem-cell-names = "soc_unique_id";
>
> aips1: bus at 30000000 {
> compatible = "fsl,aips-bus", "simple-bus";
> @@ -273,117 +303,125 @@
> #size-cells = <1>;
> ranges = <0x30000000 0x30000000 0x400000>;
>
> - sai1: sai at 30010000 {
> - #sound-dai-cells = <0>;
> - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
> - reg = <0x30010000 0x10000>;
> - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
> - <&clk IMX8MM_CLK_SAI1_ROOT>,
> - <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> - clock-names = "bus", "mclk1", "mclk2", "mclk3";
> - dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + spba2: spba-bus at 30000000 {
> + compatible = "fsl,spba-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x30000000 0x100000>;
> + ranges;
> +
> + sai1: sai at 30010000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-
> sai";
> + reg = <0x30010000 0x10000>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
> + <&clk IMX8MM_CLK_SAI1_ROOT>,
> + <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - sai2: sai at 30020000 {
> - #sound-dai-cells = <0>;
> - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
> - reg = <0x30020000 0x10000>;
> - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
> - <&clk IMX8MM_CLK_SAI2_ROOT>,
> - <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> - clock-names = "bus", "mclk1", "mclk2", "mclk3";
> - dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + sai2: sai at 30020000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-
> sai";
> + reg = <0x30020000 0x10000>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
> + <&clk IMX8MM_CLK_SAI2_ROOT>,
> + <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - sai3: sai at 30030000 {
> - #sound-dai-cells = <0>;
> - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
> - reg = <0x30030000 0x10000>;
> - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
> - <&clk IMX8MM_CLK_SAI3_ROOT>,
> - <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> - clock-names = "bus", "mclk1", "mclk2", "mclk3";
> - dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + sai3: sai at 30030000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-
> sai";
> + reg = <0x30030000 0x10000>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
> + <&clk IMX8MM_CLK_SAI3_ROOT>,
> + <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - sai5: sai at 30050000 {
> - #sound-dai-cells = <0>;
> - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
> - reg = <0x30050000 0x10000>;
> - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
> - <&clk IMX8MM_CLK_SAI5_ROOT>,
> - <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> - clock-names = "bus", "mclk1", "mclk2", "mclk3";
> - dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + sai5: sai at 30050000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-
> sai";
> + reg = <0x30050000 0x10000>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
> + <&clk IMX8MM_CLK_SAI5_ROOT>,
> + <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - sai6: sai at 30060000 {
> - #sound-dai-cells = <0>;
> - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
> - reg = <0x30060000 0x10000>;
> - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
> - <&clk IMX8MM_CLK_SAI6_ROOT>,
> - <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> - clock-names = "bus", "mclk1", "mclk2", "mclk3";
> - dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + sai6: sai at 30060000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-
> sai";
> + reg = <0x30060000 0x10000>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
> + <&clk IMX8MM_CLK_SAI6_ROOT>,
> + <&clk IMX8MM_CLK_DUMMY>, <&clk
> IMX8MM_CLK_DUMMY>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - micfil: audio-controller at 30080000 {
> - compatible = "fsl,imx8mm-micfil";
> - reg = <0x30080000 0x10000>;
> - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_PDM_IPG>,
> - <&clk IMX8MM_CLK_PDM_ROOT>,
> - <&clk IMX8MM_AUDIO_PLL1_OUT>,
> - <&clk IMX8MM_AUDIO_PLL2_OUT>,
> - <&clk IMX8MM_CLK_EXT3>;
> - clock-names = "ipg_clk", "ipg_clk_app",
> - "pll8k", "pll11k", "clkext3";
> - dmas = <&sdma2 24 25 0x80000000>;
> - dma-names = "rx";
> - status = "disabled";
> - };
> + micfil: audio-controller at 30080000 {
> + compatible = "fsl,imx8mm-micfil";
> + reg = <0x30080000 0x10000>;
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_PDM_IPG>,
> + <&clk IMX8MM_CLK_PDM_ROOT>,
> + <&clk IMX8MM_AUDIO_PLL1_OUT>,
> + <&clk IMX8MM_AUDIO_PLL2_OUT>,
> + <&clk IMX8MM_CLK_EXT3>;
> + clock-names = "ipg_clk", "ipg_clk_app",
> + "pll8k", "pll11k", "clkext3";
> + dmas = <&sdma2 24 25 0x80000000>;
> + dma-names = "rx";
> + status = "disabled";
> + };
>
> - spdif1: spdif at 30090000 {
> - compatible = "fsl,imx35-spdif";
> - reg = <0x30090000 0x10000>;
> - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
> - <&clk IMX8MM_CLK_24M>, /* rxtx0 */
> - <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
> - <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
> - <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
> - <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
> - <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
> - <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
> - <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
> - <&clk IMX8MM_CLK_DUMMY>; /* spba */
> - clock-names = "core", "rxtx0",
> - "rxtx1", "rxtx2",
> - "rxtx3", "rxtx4",
> - "rxtx5", "rxtx6",
> - "rxtx7", "spba";
> - dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> + spdif1: spdif at 30090000 {
> + compatible = "fsl,imx35-spdif";
> + reg = <0x30090000 0x10000>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core
> */
> + <&clk IMX8MM_CLK_24M>, /* rxtx0 */
> + <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
> + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
> + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
> + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
> + <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5
> */
> + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
> + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
> + <&clk IMX8MM_CLK_DUMMY>; /* spba */
> + clock-names = "core", "rxtx0",
> + "rxtx1", "rxtx2",
> + "rxtx3", "rxtx4",
> + "rxtx5", "rxtx6",
> + "rxtx7", "spba";
> + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> };
>
> gpio1: gpio at 30200000 {
> @@ -522,9 +560,17 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> + imx8mm_uid: unique-id at 410 {
> + reg = <0x4 0x8>;
> + };
> +
> cpu_speed_grade: speed-grade at 10 {
> reg = <0x10 4>;
> };
> +
> + fec_mac_address: mac-address at 90 {
> + reg = <0x90 6>;
> + };
> };
>
> anatop: anatop at 30360000 {
> @@ -556,6 +602,11 @@
> wakeup-source;
> status = "disabled";
> };
> +
> + snvs_lpgpr: snvs-lpgpr {
> + compatible = "fsl,imx8mm-snvs-lpgpr",
> + "fsl,imx7d-snvs-lpgpr";
> + };
> };
>
> clk: clock-controller at 30380000 {
> @@ -573,8 +624,7 @@
> <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
> <&clk IMX8MM_SYS_PLL3>,
> <&clk IMX8MM_VIDEO_PLL1>,
> - <&clk IMX8MM_AUDIO_PLL1>,
> - <&clk IMX8MM_AUDIO_PLL2>;
> + <&clk IMX8MM_AUDIO_PLL1>;
> assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
> <&clk IMX8MM_ARM_PLL_OUT>,
> <&clk IMX8MM_SYS_PLL3_OUT>,
> @@ -584,8 +634,7 @@
> <400000000>,
> <750000000>,
> <594000000>,
> - <393216000>,
> - <361267200>;
> + <393216000>;
> };
>
> src: reset-controller at 30390000 {
> @@ -598,6 +647,7 @@
> gpc: gpc at 303a0000 {
> compatible = "fsl,imx8mm-gpc";
> reg = <0x303a0000 0x10000>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-parent = <&gic>;
> interrupt-controller;
> #interrupt-cells = <3>;
> @@ -610,12 +660,15 @@
> #power-domain-cells = <0>;
> reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
> clocks = <&clk IMX8MM_CLK_USB_BUS>;
> + assigned-clocks = <&clk
> IMX8MM_CLK_USB_BUS>;
> + assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL2_500M>;
> };
>
> pgc_pcie: power-domain at 1 {
> #power-domain-cells = <0>;
> reg = <IMX8MM_POWER_DOMAIN_PCIE>;
> power-domains = <&pgc_hsiomix>;
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
> };
>
> pgc_otg1: power-domain at 2 {
> @@ -634,32 +687,63 @@
> #power-domain-cells = <0>;
> reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
> clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> - <&clk IMX8MM_CLK_GPU_AHB>;
> + <&clk IMX8MM_CLK_GPU_AHB>;
> + assigned-clocks = <&clk
> IMX8MM_CLK_GPU_AXI>,
> + <&clk
> IMX8MM_CLK_GPU_AHB>;
> + assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL1_800M>,
> + <&clk
> IMX8MM_SYS_PLL1_800M>;
> + assigned-clock-rates = <800000000>,
> <400000000>;
> };
>
> pgc_gpu: power-domain at 5 {
> #power-domain-cells = <0>;
> reg = <IMX8MM_POWER_DOMAIN_GPU>;
> clocks = <&clk IMX8MM_CLK_GPU_AHB>,
> - <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> - <&clk IMX8MM_CLK_GPU2D_ROOT>,
> - <&clk IMX8MM_CLK_GPU3D_ROOT>;
> + <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> + <&clk IMX8MM_CLK_GPU2D_ROOT>,
> + <&clk IMX8MM_CLK_GPU3D_ROOT>;
> resets = <&src IMX8MQ_RESET_GPU_RESET>;
> power-domains = <&pgc_gpumix>;
> };
>
> - dispmix_pd: power-domain at 10 {
> + pgc_vpumix: power-domain at 6 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
> + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
> + assigned-clocks = <&clk
> IMX8MM_CLK_VPU_BUS>;
> + assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL1_800M>;
> + };
> +
> + pgc_vpu_g1: power-domain at 7 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
> + };
> +
> + pgc_vpu_g2: power-domain at 8 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
> + };
> +
> + pgc_vpu_h1: power-domain at 9 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
> + };
> +
> + pgc_dispmix: power-domain at 10 {
> #power-domain-cells = <0>;
> reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
> - clocks = <&clk IMX8MM_CLK_DISP_ROOT>,
> - <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
> - <&clk IMX8MM_CLK_DISP_APB_ROOT>;
> + clocks = <&clk
> IMX8MM_CLK_DISP_APB_ROOT>,
> + <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
> + assigned-clocks = <&clk
> IMX8MM_CLK_DISP_AXI>,
> + <&clk
> IMX8MM_CLK_DISP_APB>;
> + assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL2_1000M>,
> + <&clk
> IMX8MM_SYS_PLL1_800M>;
> + assigned-clock-rates = <500000000>,
> <200000000>;
> };
>
> - mipi_pd: power-domain at 11 {
> + pgc_mipi: power-domain at 11 {
> #power-domain-cells = <0>;
> reg = <IMX8MM_POWER_DOMAIN_MIPI>;
> - power-domains = <&dispmix_pd>;
> };
> };
> };
> @@ -679,7 +763,7 @@
> clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
> <&clk IMX8MM_CLK_PWM1_ROOT>;
> clock-names = "ipg", "per";
> - #pwm-cells = <2>;
> + #pwm-cells = <3>;
> status = "disabled";
> };
>
> @@ -690,7 +774,7 @@
> clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
> <&clk IMX8MM_CLK_PWM2_ROOT>;
> clock-names = "ipg", "per";
> - #pwm-cells = <2>;
> + #pwm-cells = <3>;
> status = "disabled";
> };
>
> @@ -701,7 +785,7 @@
> clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
> <&clk IMX8MM_CLK_PWM3_ROOT>;
> clock-names = "ipg", "per";
> - #pwm-cells = <2>;
> + #pwm-cells = <3>;
> status = "disabled";
> };
>
> @@ -712,7 +796,7 @@
> clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
> <&clk IMX8MM_CLK_PWM4_ROOT>;
> clock-names = "ipg", "per";
> - #pwm-cells = <2>;
> + #pwm-cells = <3>;
> status = "disabled";
One of those 3 "pwm-cells" gives following warnings:
arch/arm/dts/imx8mm-data-modul-edm-sbc.dtb: Warning (pwms_property): /backlight:pwms: property size (12) too small for cell size 3
arch/arm/dts/imx8mm-evk.dtb: Warning (pwms_property): /backlight:pwms: property size (12) too small for cell size 3
arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dtb: Warning (pwms_property): /backlight:pwms: property size (12) too small for cell size 3
I guess there's a bit more needed here, than just imx8mm.dtsi...
> };
>
> @@ -733,80 +817,88 @@
> ranges = <0x30800000 0x30800000 0x400000>,
> <0x8000000 0x8000000 0x10000000>;
>
> - ecspi1: spi at 30820000 {
> - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> + spba1: spba-bus at 30800000 {
> + compatible = "fsl,spba-bus", "simple-bus";
> #address-cells = <1>;
> - #size-cells = <0>;
> - reg = <0x30820000 0x10000>;
> - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
> - <&clk IMX8MM_CLK_ECSPI1_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + #size-cells = <1>;
> + reg = <0x30800000 0x100000>;
> + ranges;
>
> - ecspi2: spi at 30830000 {
> - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - reg = <0x30830000 0x10000>;
> - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
> - <&clk IMX8MM_CLK_ECSPI2_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + ecspi1: spi at 30820000 {
> + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-
> ecspi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x30820000 0x10000>;
> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
> + <&clk IMX8MM_CLK_ECSPI1_ROOT>;
> + clock-names = "ipg", "per";
> + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - ecspi3: spi at 30840000 {
> - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - reg = <0x30840000 0x10000>;
> - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
> - <&clk IMX8MM_CLK_ECSPI3_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + ecspi2: spi at 30830000 {
> + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-
> ecspi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x30830000 0x10000>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
> + <&clk IMX8MM_CLK_ECSPI2_ROOT>;
> + clock-names = "ipg", "per";
> + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - uart1: serial at 30860000 {
> - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
> - reg = <0x30860000 0x10000>;
> - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
> - <&clk IMX8MM_CLK_UART1_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + ecspi3: spi at 30840000 {
> + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-
> ecspi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x30840000 0x10000>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
> + <&clk IMX8MM_CLK_ECSPI3_ROOT>;
> + clock-names = "ipg", "per";
> + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - uart3: serial at 30880000 {
> - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
> - reg = <0x30880000 0x10000>;
> - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
> - <&clk IMX8MM_CLK_UART3_ROOT>;
> - clock-names = "ipg", "per";
> - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> + uart1: serial at 30860000 {
> + compatible = "fsl,imx8mm-uart", "fsl,imx6q-
> uart";
> + reg = <0x30860000 0x10000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
> + <&clk IMX8MM_CLK_UART1_ROOT>;
> + clock-names = "ipg", "per";
> + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> - uart2: serial at 30890000 {
> - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
> - reg = <0x30890000 0x10000>;
> - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
> - <&clk IMX8MM_CLK_UART2_ROOT>;
> - clock-names = "ipg", "per";
> - status = "disabled";
> + uart3: serial at 30880000 {
> + compatible = "fsl,imx8mm-uart", "fsl,imx6q-
> uart";
> + reg = <0x30880000 0x10000>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
> + <&clk IMX8MM_CLK_UART3_ROOT>;
> + clock-names = "ipg", "per";
> + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart2: serial at 30890000 {
> + compatible = "fsl,imx8mm-uart", "fsl,imx6q-
> uart";
> + reg = <0x30890000 0x10000>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
> + <&clk IMX8MM_CLK_UART2_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> };
>
> crypto: crypto at 30900000 {
> @@ -824,6 +916,7 @@
> compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x1000 0x1000>;
> interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> sec_jr1: jr at 2000 {
> @@ -908,7 +1001,7 @@
> <&clk IMX8MM_CLK_USDHC1_ROOT>;
> clock-names = "ipg", "ahb", "per";
> fsl,tuning-start-tap = <20>;
> - fsl,tuning-step= <2>;
> + fsl,tuning-step = <2>;
> bus-width = <4>;
> status = "disabled";
> };
> @@ -922,7 +1015,7 @@
> <&clk IMX8MM_CLK_USDHC2_ROOT>;
> clock-names = "ipg", "ahb", "per";
> fsl,tuning-start-tap = <20>;
> - fsl,tuning-step= <2>;
> + fsl,tuning-step = <2>;
> bus-width = <4>;
> status = "disabled";
> };
> @@ -936,7 +1029,7 @@
> <&clk IMX8MM_CLK_USDHC3_ROOT>;
> clock-names = "ipg", "ahb", "per";
> fsl,tuning-start-tap = <20>;
> - fsl,tuning-step= <2>;
> + fsl,tuning-step = <2>;
> bus-width = <4>;
> status = "disabled";
> };
> @@ -950,7 +1043,7 @@
> interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
> <&clk IMX8MM_CLK_QSPI_ROOT>;
> - clock-names = "fspi", "fspi_en";
> + clock-names = "fspi_en", "fspi";
> status = "disabled";
> };
>
> @@ -966,7 +1059,7 @@
> };
>
> fec1: ethernet at 30be0000 {
> - compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
> + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec",
> "fsl,imx6sx-fec";
> reg = <0x30be0000 0x10000>;
> interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> @@ -982,13 +1075,17 @@
> assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
> <&clk IMX8MM_CLK_ENET_TIMER>,
> <&clk IMX8MM_CLK_ENET_REF>,
> - <&clk IMX8MM_CLK_ENET_TIMER>;
> + <&clk IMX8MM_CLK_ENET_PHY_REF>;
> assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> <&clk IMX8MM_SYS_PLL2_100M>,
> - <&clk IMX8MM_SYS_PLL2_125M>;
> - assigned-clock-rates = <0>, <0>, <125000000>,
> <100000000>;
> + <&clk IMX8MM_SYS_PLL2_125M>,
> + <&clk IMX8MM_SYS_PLL2_50M>;
> + assigned-clock-rates = <0>, <100000000>, <125000000>,
> <0>;
> fsl,num-tx-queues = <3>;
> fsl,num-rx-queues = <3>;
> + nvmem-cells = <&fec_mac_address>;
> + nvmem-cell-names = "mac-address";
> + fsl,stop-mode = <&gpr 0x10 3>;
> status = "disabled";
> };
>
> @@ -1001,6 +1098,84 @@
> #size-cells = <1>;
> ranges = <0x32c00000 0x32c00000 0x400000>;
>
> + csi: csi at 32e20000 {
> + compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
> + reg = <0x32e20000 0x1000>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
> + clock-names = "mclk";
> + power-domains = <&disp_blk_ctrl
> IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
> + status = "disabled";
> +
> + port {
> + csi_in: endpoint {
> + remote-endpoint =
> <&imx8mm_mipi_csi_out>;
> + };
> + };
> + };
> +
> + disp_blk_ctrl: blk-ctrl at 32e28000 {
> + compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
> + reg = <0x32e28000 0x100>;
> + power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
> + <&pgc_dispmix>, <&pgc_mipi>,
> + <&pgc_mipi>;
> + power-domain-names = "bus", "csi-bridge",
> + "lcdif", "mipi-dsi",
> + "mipi-csi";
> + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
> + <&clk IMX8MM_CLK_DISP_APB_ROOT>,
> + <&clk IMX8MM_CLK_CSI1_ROOT>,
> + <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
> + <&clk IMX8MM_CLK_DISP_APB_ROOT>,
> + <&clk IMX8MM_CLK_DISP_ROOT>,
> + <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>,
> + <&clk IMX8MM_CLK_CSI1_CORE>,
> + <&clk IMX8MM_CLK_CSI1_PHY_REF>;
> + clock-names = "csi-bridge-axi","csi-bridge-apb",
> + "csi-bridge-core", "lcdif-axi",
> + "lcdif-apb", "lcdif-pix",
> + "dsi-pclk", "dsi-ref",
> + "csi-aclk", "csi-pclk";
> + #power-domain-cells = <1>;
> + };
> +
> + mipi_csi: mipi-csi at 32e30000 {
> + compatible = "fsl,imx8mm-mipi-csi2";
> + reg = <0x32e30000 0x1000>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
> + <&clk IMX8MM_CLK_CSI1_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
> + <&clk IMX8MM_SYS_PLL2_1000M>;
> + clock-frequency = <333000000>;
> + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
> + <&clk IMX8MM_CLK_CSI1_ROOT>,
> + <&clk IMX8MM_CLK_CSI1_PHY_REF>,
> + <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
> + clock-names = "pclk", "wrap", "phy", "axi";
> + power-domains = <&disp_blk_ctrl
> IMX8MM_DISPBLK_PD_MIPI_CSI>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + };
> +
> + port at 1 {
> + reg = <1>;
> +
> + imx8mm_mipi_csi_out: endpoint {
> + remote-endpoint = <&csi_in>;
> + };
> + };
> + };
> + };
> +
> usbotg1: usb at 32e40000 {
> compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
> reg = <0x32e40000 0x200>;
> @@ -1116,6 +1291,72 @@
> status = "disabled";
> };
>
> + gpu_3d: gpu at 38000000 {
> + compatible = "vivante,gc";
> + reg = <0x38000000 0x8000>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_GPU_AHB>,
> + <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> + <&clk IMX8MM_CLK_GPU3D_ROOT>,
> + <&clk IMX8MM_CLK_GPU3D_ROOT>;
> + clock-names = "reg", "bus", "core", "shader";
> + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
> + <&clk IMX8MM_GPU_PLL_OUT>;
> + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
> + assigned-clock-rates = <0>, <1000000000>;
> + power-domains = <&pgc_gpu>;
> + };
> +
> + gpu_2d: gpu at 38008000 {
> + compatible = "vivante,gc";
> + reg = <0x38008000 0x8000>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_GPU_AHB>,
> + <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> + <&clk IMX8MM_CLK_GPU2D_ROOT>;
> + clock-names = "reg", "bus", "core";
> + assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
> + <&clk IMX8MM_GPU_PLL_OUT>;
> + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
> + assigned-clock-rates = <0>, <1000000000>;
> + power-domains = <&pgc_gpu>;
> + };
> +
> + vpu_g1: video-codec at 38300000 {
> + compatible = "nxp,imx8mm-vpu-g1";
> + reg = <0x38300000 0x10000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
> + };
> +
> + vpu_g2: video-codec at 38310000 {
> + compatible = "nxp,imx8mq-vpu-g2";
> + reg = <0x38310000 0x10000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
> + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
> + };
> +
> + vpu_blk_ctrl: blk-ctrl at 38330000 {
> + compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
> + reg = <0x38330000 0x100>;
> + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
> + <&pgc_vpu_g2>, <&pgc_vpu_h1>;
> + power-domain-names = "bus", "g1", "g2", "h1";
> + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
> + <&clk IMX8MM_CLK_VPU_G2_ROOT>,
> + <&clk IMX8MM_CLK_VPU_H1_ROOT>;
> + clock-names = "g1", "g2", "h1";
> + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
> + <&clk IMX8MM_CLK_VPU_G2>;
> + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
> + <&clk IMX8MM_VPU_PLL_OUT>;
> + assigned-clock-rates = <600000000>,
> + <600000000>;
> + #power-domain-cells = <1>;
> + };
> +
> gic: interrupt-controller at 38800000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>, /* GIC Dist */
> diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-
> bindings/power/imx8mm-power.h
> index fc9c2e16aadc..648938f24c8e 100644
> --- a/include/dt-bindings/power/imx8mm-power.h
> +++ b/include/dt-bindings/power/imx8mm-power.h
> @@ -19,4 +19,13 @@
> #define IMX8MM_POWER_DOMAIN_DISPMIX 10
> #define IMX8MM_POWER_DOMAIN_MIPI 11
>
> +#define IMX8MM_VPUBLK_PD_G1 0
> +#define IMX8MM_VPUBLK_PD_G2 1
> +#define IMX8MM_VPUBLK_PD_H1 2
> +
> +#define IMX8MM_DISPBLK_PD_CSI_BRIDGE 0
> +#define IMX8MM_DISPBLK_PD_LCDIF 1
> +#define IMX8MM_DISPBLK_PD_MIPI_DSI 2
> +#define IMX8MM_DISPBLK_PD_MIPI_CSI 3
> +
> #endif
> --
> 2.25.1
Regards,
Andrey
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