cache: l2x0: Fix incorrect behavior if the latency is 1 cycle

[haifeng.li at timesintelli.com]

According to the PL310 TRM, 0 in the latency fields(setup/read/write)
indicates 1 cycle of latency for Tag and Data RAM latency control
registers. If we want to set 1 cycle of latency, we need to clear
the field actually. The TRM is as below:
https://developer.arm.com/documentation/ddi0246/h/programmers-model/register
-descriptions/tag-and-data-ram-latency-control-registers

Signed-off-by: Haifeng Li <haifeng.li at timesintelli.com>

drivers/cache/cache-l2x0.c | 6 ++++++
1 file changed, 6 insertions(+)
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