Re: cache: l2x0: Fix incorrect behavior if the latency is 1 cycle

[Haifeng Li]

please ignore this email. I will re-send it with patch inline.

Thanks,
Haifeng.
------------------------------------------------------------------
From:Haifeng Li <haifeng.li at timesintelli.com>
Sent At:2022 Mar. 18 (Fri.) 19:28
To:dinguyen <dinguyen at kernel.org>; u-boot <u-boot at lists.denx.de>
Cc:Haifeng Li <haifeng.li at timesintelli.com>
Subject:cache: l2x0: Fix incorrect behavior if the latency is 1 cycle

According to the PL310 TRM, 0 in the latency fields(setup/read/write)
indicates 1 cycle of latency for Tag and Data RAM latency control
registers. If we want to set 1 cycle of latency, we need to clear
the field actually. The TRM is as below:
https://developer.arm.com/documentation/ddi0246/h/programmers-model/register
-descriptions/tag-and-data-ram-latency-control-registers

Signed-off-by: Haifeng Li <haifeng.li at timesintelli.com>

drivers/cache/cache-l2x0.c | 6 ++++++
1 file changed, 6 insertions(+)