[PATCH 2/5] imx8mm-cl-iot-gate: Retrieve the DDR type from EEPROM

[Tim Harvey]

On Sat, Mar 19, 2022 at 5:23 AM Fabio Estevam <festevam at gmail.com> wrote:
>
> From: Fabio Estevam <festevam at denx.de>
>
> Currently, the DDR type is retrieved by iteracting inside an array
> of possible DDR types.
>
> This may take saveral attempts, which slows the overall U-Boot process
> and does not provide a good user experience:
>
> U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000)
> DDRINFO: Cfg attempt: [ 1/6 ]
> DDRINFO(M): mr5-8 [ 0xff000010 ]
> DDRINFO(T): mr5-8 [ 0x5000010 ]
> resetting ...
>
> U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000)
> DDRINFO: Cfg attempt: [ 2/6 ]
> DDRINFO(M): mr5-8 [ 0xff000010 ]
> DDRINFO(T): mr5-8 [ 0x1061010 ]
> resetting ...
>
> U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000)
> DDRINFO: Cfg attempt: [ 3/6 ]
> DDRINFO(M): mr5-8 [ 0xff000010 ]
> DDRINFO(T): mr5-8 [ 0xff000010 ]
> Normal Boot
> WDT:   Not starting
> Trying to boot from MMC2
> NOTICE:  BL31: v2.5(release):v2.5
> NOTICE:  BL31: Built : 07:12:44, Jan 24 2022
>
> Improve the boot time by retrieving the correct DDR information from
> the EEPROM:
>
> U-Boot SPL 2022.04-rc4-00045-g6d02bc40d58c (Mar 19 2022 - 08:22:29 -0300)
> DDRINFO(D): Kingston 4096G
> DDRINFO(M): mr5-8 [ 0xff000010 ]
> DDRINFO(E): mr5-8 [ 0xff000010 ]
> Normal Boot
> WDT:   Started watchdog at 30280000 with servicing (60s timeout)
> Trying to boot from MMC2
> NOTICE:  BL31: v2.5(release):v2.5
> NOTICE:  BL31: Built : 22:28:11, Mar 15 2022
>
> Based on the original code from Compulab's U-Boot.
>
> Tested on a imx8mm-cl-iot-gate board populated with 4GB of RAM.
>
> Signed-off-by: Fabio Estevam <festevam at denx.de>
> ---
>  board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 24 ++++++++++++++++++---
>  board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h |  5 +++++
>  2 files changed, 26 insertions(+), 3 deletions(-)
>
> diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
> index 42dd0dbf18fa..5b93491923e9 100644
> --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
> +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
> @@ -22,6 +22,8 @@
>  #include <asm/mach-imx/gpio.h>
>  #include "ddr.h"
>
> +#include <linux/delay.h>
> +
>  static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
>  {
>         unsigned int tmp;
> @@ -137,10 +139,11 @@ void spl_dram_init_compulab(void)
>                 (struct lpddr4_tcm_desc *)SPL_TCM_DATA;
>
>         if (lpddr4_tcm_desc->sign != DEFAULT) {
> -               /* if not in tcm scan mode */
> +               /* get ddr type from the eeprom if not in tcm scan mode */
> +               ddr_info = cl_eeprom_get_ddrinfo();
>                 for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) {
>                         if (lpddr4_array[i].id == ddr_info &&
> -                           lpddr4_array[i].subind == 0xff) {
> +                       lpddr4_array[i].subind == cl_eeprom_get_subind()) {
>                                 ddr_found = 1;
>                                 break;
>                         }
> @@ -198,10 +201,25 @@ void spl_dram_init_compulab(void)
>
>         SPL_TCM_FINI;
>
> +       if (ddr_found == 0) {
> +               /* Update eeprom */
> +               cl_eeprom_set_ddrinfo(ddr_info_mrr);
> +               mdelay(10);
> +               ddr_info = cl_eeprom_get_ddrinfo();
> +               mdelay(10);
> +               cl_eeprom_set_subind(lpddr4_array[i].subind);
> +               /* make sure that the ddr_info has reached the eeprom */
> +               printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n", ddr_info);
> +               if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind() != lpddr4_array[i].subind) {
> +                       printf("DDRINFO(EEPROM): make sure that the eeprom is accessible\n");
> +                       printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x51 0x40 0x50\n");
> +               }
> +       }
> +
>         /* Pass the dram size to th U-Boot through the tcm memory */
>         { /* To figure out what to store into the TCM buffer */
>           /* For debug purpouse only. To override the real memsize */
> -               unsigned int ddr_tcm_size = 0;
> +               unsigned int ddr_tcm_size = cl_eeprom_get_osize();
>
>                 if (ddr_tcm_size == 0 || ddr_tcm_size == -1)
>                         ddr_tcm_size = lpddr4_array[i].size;
> diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
> index 59c18911592e..f7d4fdc1016a 100644
> --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
> +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
> @@ -23,4 +23,9 @@ struct lpddr4_tcm_desc {
>         unsigned int count;
>  };
>
> +u32 cl_eeprom_get_ddrinfo(void);
> +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo);
> +u32 cl_eeprom_get_subind(void);
> +u32 cl_eeprom_set_subind(u32 subind);
> +u32 cl_eeprom_get_osize(void);
>  #endif
> --
> 2.25.1
>

Fabio,

This seems like a strange approach if you have an EEPROM that tells
you which memory you have. If you know which memory why don't you just
use the correct struct dram_timing_info directly from the lpddr4_array
instead of looping through the array?

For imx8mm_venice boards the EEPROM on the board provides me with DRAM
details. Currently I only need DRAM size to be able to pick from
several dram_timing_info options [1].

Best Regards,

Tim
[1] https://elixir.bootlin.com/u-boot/latest/source/board/gateworks/venice/spl.c#L39