[PATCH v2 2/2] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS
Kever Yang
kever.yang at rock-chips.com
Wed Jul 26 11:13:43 CEST 2023
On 2023/5/20 19:20, Tianling Shen wrote:
> The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
> the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type
> changed from DDR4 to LPDDR3.
>
> The device tree is taken from kernel v6.4-rc1.
>
> Signed-off-by: Tianling Shen <cnsztl at gmail.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>
Thanks,
- Kever
> ---
>
> Changes in v2:
> * Rebased upon the latest git HEAD
> * Fixed memory profile (rk3328-sdram-lpddr3-1600.dtsi -> rk3328-sdram-lpddr3-666.dtsi)
> * Removed kernel link from commit message
>
> ---
> arch/arm/dts/Makefile | 1 +
> .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++++++
> arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 40 ++++++
> board/rockchip/evb_rk3328/MAINTAINERS | 6 +
> configs/orangepi-r1-plus-lts-rk3328_defconfig | 114 ++++++++++++++++++
> 5 files changed, 207 insertions(+)
> create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
> create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 9d189788aa..425bf4e7a9 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
> rk3328-nanopi-r2c.dtb \
> rk3328-nanopi-r2s.dtb \
> rk3328-orangepi-r1-plus.dtb \
> + rk3328-orangepi-r1-plus-lts.dtb \
> rk3328-roc-cc.dtb \
> rk3328-rock64.dtb \
> rk3328-rock-pi-e.dtb
> diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
> new file mode 100644
> index 0000000000..ebe33e48cb
> --- /dev/null
> +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
> @@ -0,0 +1,46 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
> + * (C) Copyright 2020 David Bauer
> + */
> +
> +#include "rk3328-u-boot.dtsi"
> +#include "rk3328-sdram-lpddr3-666.dtsi"
> +/ {
> + chosen {
> + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
> + };
> +};
> +
> +&gpio0 {
> + bootph-pre-ram;
> +};
> +
> +&pinctrl {
> + bootph-pre-ram;
> +};
> +
> +&sdmmc0m1_pin {
> + bootph-pre-ram;
> +};
> +
> +&pcfg_pull_up_4ma {
> + bootph-pre-ram;
> +};
> +
> +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
> +&vcc_sd {
> + bootph-pre-ram;
> +};
> +
> +&gmac2io {
> + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
> + snps,reset-active-low;
> + snps,reset-delays-us = <0 10000 50000>;
> +};
> +
> +&spi0 {
> + spi_flash: spiflash at 0 {
> + bootph-all;
> + };
> +};
> diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
> new file mode 100644
> index 0000000000..5d7d567283
> --- /dev/null
> +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Copyright (c) 2016 Xunlong Software. Co., Ltd.
> + * (http://www.orangepi.org)
> + *
> + * Copyright (c) 2021-2023 Tianling Shen <cnsztl at gmail.com>
> + */
> +
> +/dts-v1/;
> +#include "rk3328-orangepi-r1-plus.dts"
> +
> +/ {
> + model = "Xunlong Orange Pi R1 Plus LTS";
> + compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
> +};
> +
> +&gmac2io {
> + phy-handle = <&yt8531c>;
> + tx_delay = <0x19>;
> + rx_delay = <0x05>;
> +
> + mdio {
> + /delete-node/ ethernet-phy at 1;
> +
> + yt8531c: ethernet-phy at 0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> +
> + motorcomm,clk-out-frequency-hz = <125000000>;
> + motorcomm,keep-pll-enabled;
> + motorcomm,auto-sleep-disabled;
> +
> + pinctrl-0 = <ð_phy_reset_pin>;
> + pinctrl-names = "default";
> + reset-assert-us = <15000>;
> + reset-deassert-us = <50000>;
> + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS
> index 91dc6b58cf..8a19eb373d 100644
> --- a/board/rockchip/evb_rk3328/MAINTAINERS
> +++ b/board/rockchip/evb_rk3328/MAINTAINERS
> @@ -24,6 +24,12 @@ S: Maintained
> F: configs/orangepi-r1-plus-rk3328_defconfig
> F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
>
> +ORANGEPI-R1-PLUS-LTS-RK3328
> +M: Tianling Shen <cnsztl at gmail.com>
> +S: Maintained
> +F: configs/orangepi-r1-plus-lts-rk3328_defconfig
> +F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
> +
> ROC-RK3328-CC
> M: Loic Devulder <ldevulder at suse.com>
> M: Chen-Yu Tsai <wens at csie.org>
> diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
> new file mode 100644
> index 0000000000..59a28e5209
> --- /dev/null
> +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
> @@ -0,0 +1,114 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=24000000
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_TEXT_BASE=0x00200000
> +CONFIG_SPL_GPIO=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
> +CONFIG_ENV_OFFSET=0x3F8000
> +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
> +CONFIG_DM_RESET=y
> +CONFIG_ROCKCHIP_RK3328=y
> +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
> +CONFIG_TPL_LIBCOMMON_SUPPORT=y
> +CONFIG_TPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC=y
> +CONFIG_SPL_STACK_R_ADDR=0x600000
> +CONFIG_SPL_STACK=0x400000
> +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
> +CONFIG_DEBUG_UART_BASE=0xFF130000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_SYS_LOAD_ADDR=0x800800
> +CONFIG_DEBUG_UART=y
> +# CONFIG_ANDROID_BOOT_IMAGE is not set
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_MISC_INIT_R=y
> +CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_PAD_TO=0x7f8000
> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> +CONFIG_SPL_BSS_START_ADDR=0x2000000
> +CONFIG_SPL_BSS_MAX_SIZE=0x2000
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_I2C=y
> +CONFIG_SPL_POWER=y
> +CONFIG_SPL_ATF=y
> +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
> +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_TIME=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_TPL_OF_CONTROL=y
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_TPL_OF_PLATDATA=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SYS_MMC_ENV_DEV=1
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_TPL_DM=y
> +CONFIG_REGMAP=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_TPL_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_TPL_SYSCON=y
> +CONFIG_CLK=y
> +CONFIG_SPL_CLK=y
> +CONFIG_FASTBOOT_BUF_ADDR=0x800800
> +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_SF_DEFAULT_SPEED=20000000
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_ETH_DESIGNWARE=y
> +CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_DM_PMIC=y
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_SPL_PMIC_RK8XX=y
> +CONFIG_SPL_DM_REGULATOR=y
> +CONFIG_REGULATOR_PWM=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_SPL_DM_REGULATOR_FIXED=y
> +CONFIG_REGULATOR_RK8XX=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_TPL_RAM=y
> +CONFIG_BAUDRATE=1500000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550_MEM32=y
> +CONFIG_ROCKCHIP_SPI=y
> +CONFIG_SYSINFO=y
> +CONFIG_SYSRESET=y
> +# CONFIG_TPL_SYSRESET is not set
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_GENERIC=y
> +CONFIG_USB_DWC2=y
> +CONFIG_USB_DWC3=y
> +# CONFIG_USB_DWC3_GADGET is not set
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DWC2_OTG=y
> +CONFIG_SPL_TINY_MEMSET=y
> +CONFIG_TPL_TINY_MEMSET=y
> +CONFIG_ERRNO_STR=y
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