[PATCH v1 1/2] arch: riscv: jh7110: Split the zeroing of L2 LIM on JH7110

[yanhong wang]

On 2023/5/21 19:42, Bo Gan wrote:
> Hi Yanhong and others,
> 
> I've made up my own version and addressed my concerns in this patch:
> 
> https://patchwork.ozlabs.org/project/uboot/patch/1684668616-358043-1-git-send-email-ganboing@gmail.com/
> 

Hi Bo Gan,

Sorry very much, when I submitted this patch, I didn't confirm that you had already submitted it, 
so the current situation has occurred. I will terminate the submission of this patch.

> Some descriptions would be similar, as they are from my previous response to Heinrich:
> https://lists.denx.de/pipermail/u-boot/2023-May/518359.html
> 

The description of L2 LIM in the U74 datasheet is much the same as your previous 
response to Heinrich, so your previous response is referenced in the description
section of this patch. This patch submission does not include a cover letter, and
the content of the reference is not explained, I am very sorry.	

> Also please note that this patch is based on
> https://patchwork.ozlabs.org/project/uboot/patch/1684650044-313122-1-git-send-email-ganboing@gmail.com/
> 
> It addressed another issue with riscv stack initialization on all platforms.
> Please let me know if you have any suggestions. Thanks!