[PATCH 3/5] arm64: zynqmp: Align nvmem-fw node with dt-schema
Michal Simek
michal.simek at amd.com
Thu Feb 1 13:38:42 CET 2024
Node name has to be renamed to be aligned with dt-schema and also
xlnx,zynqmp-nvmem-fw switched to fixed-layout.
Signed-off-by: Michal Simek <michal.simek at amd.com>
---
arch/arm/dts/zynqmp.dtsi | 125 ++++++++++++++++++++-------------------
1 file changed, 64 insertions(+), 61 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index e539fa329e19..855a97077d98 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -207,68 +207,71 @@
mbox-names = "tx", "rx";
};
- nvmem-firmware {
+ soc-nvmem {
compatible = "xlnx,zynqmp-nvmem-fw";
- #address-cells = <1>;
- #size-cells = <1>;
-
- soc_revision: soc-revision at 0 {
- reg = <0x0 0x4>;
- };
- /* efuse access */
- efuse_dna: efuse-dna at c {
- reg = <0xc 0xc>;
- };
- efuse_usr0: efuse-usr0 at 20 {
- reg = <0x20 0x4>;
- };
- efuse_usr1: efuse-usr1 at 24 {
- reg = <0x24 0x4>;
- };
- efuse_usr2: efuse-usr2 at 28 {
- reg = <0x28 0x4>;
- };
- efuse_usr3: efuse-usr3 at 2c {
- reg = <0x2c 0x4>;
- };
- efuse_usr4: efuse-usr4 at 30 {
- reg = <0x30 0x4>;
- };
- efuse_usr5: efuse-usr5 at 34 {
- reg = <0x34 0x4>;
- };
- efuse_usr6: efuse-usr6 at 38 {
- reg = <0x38 0x4>;
- };
- efuse_usr7: efuse-usr7 at 3c {
- reg = <0x3c 0x4>;
- };
- efuse_miscusr: efuse-miscusr at 40 {
- reg = <0x40 0x4>;
- };
- efuse_chash: efuse-chash at 50 {
- reg = <0x50 0x4>;
- };
- efuse_pufmisc: efuse-pufmisc at 54 {
- reg = <0x54 0x4>;
- };
- efuse_sec: efuse-sec at 58 {
- reg = <0x58 0x4>;
- };
- efuse_spkid: efuse-spkid at 5c {
- reg = <0x5c 0x4>;
- };
- efuse_aeskey: efuse-aeskey at 60 {
- reg = <0x60 0x20>;
- };
- efuse_ppk0hash: efuse-ppk0hash at a0 {
- reg = <0xa0 0x30>;
- };
- efuse_ppk1hash: efuse-ppk1hash at d0 {
- reg = <0xd0 0x30>;
- };
- efuse_pufuser: efuse-pufuser at 100 {
- reg = <0x100 0x7F>;
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc_revision: soc-revision at 0 {
+ reg = <0x0 0x4>;
+ };
+ /* efuse access */
+ efuse_dna: efuse-dna at c {
+ reg = <0xc 0xc>;
+ };
+ efuse_usr0: efuse-usr0 at 20 {
+ reg = <0x20 0x4>;
+ };
+ efuse_usr1: efuse-usr1 at 24 {
+ reg = <0x24 0x4>;
+ };
+ efuse_usr2: efuse-usr2 at 28 {
+ reg = <0x28 0x4>;
+ };
+ efuse_usr3: efuse-usr3 at 2c {
+ reg = <0x2c 0x4>;
+ };
+ efuse_usr4: efuse-usr4 at 30 {
+ reg = <0x30 0x4>;
+ };
+ efuse_usr5: efuse-usr5 at 34 {
+ reg = <0x34 0x4>;
+ };
+ efuse_usr6: efuse-usr6 at 38 {
+ reg = <0x38 0x4>;
+ };
+ efuse_usr7: efuse-usr7 at 3c {
+ reg = <0x3c 0x4>;
+ };
+ efuse_miscusr: efuse-miscusr at 40 {
+ reg = <0x40 0x4>;
+ };
+ efuse_chash: efuse-chash at 50 {
+ reg = <0x50 0x4>;
+ };
+ efuse_pufmisc: efuse-pufmisc at 54 {
+ reg = <0x54 0x4>;
+ };
+ efuse_sec: efuse-sec at 58 {
+ reg = <0x58 0x4>;
+ };
+ efuse_spkid: efuse-spkid at 5c {
+ reg = <0x5c 0x4>;
+ };
+ efuse_aeskey: efuse-aeskey at 60 {
+ reg = <0x60 0x20>;
+ };
+ efuse_ppk0hash: efuse-ppk0hash at a0 {
+ reg = <0xa0 0x30>;
+ };
+ efuse_ppk1hash: efuse-ppk1hash at d0 {
+ reg = <0xd0 0x30>;
+ };
+ efuse_pufuser: efuse-pufuser at 100 {
+ reg = <0x100 0x7F>;
+ };
};
};
--
2.36.1
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