[PATCH v2] clk: fixed-rate: Use "clock-output-names" to name fixed clocks

[Fabio Estevam]

On Thu, Apr 24, 2025 at 11:35 PM Fabio Estevam <festevam at gmail.com> wrote:

> I haven't had a chance to debug this issue yet.

I applied this debug patch:

--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1539,6 +1539,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
        }

        priv->sdhc_clk = clk_get_rate(&priv->per_clk);
+       printf("****** sdhc clk is %d\n", priv->sdhc_clk);
 #else
        init_clk_usdhc(dev_seq(dev));

With the top-of-tree U-Boot, SPL calculates the wrong sdhc_clk on the
imx8mm-evk:

U-Boot SPL 2025.04-01380-ga9820e12db18-dirty (Apr 25 2025 - 09:40:45 -0300)
No pmic
WDT:   Started watchdog at 30280000 with servicing every 1000ms (60s timeout)
SEC0:  RNG instantiated
Trying to boot from MMC1
****** sdhc clk is 204522251

If I revert b4734c9c333b ("clk: imx: Convert clock-osc-* back to
osc_*"), the clock is calculated correctly:

U-Boot 2025.04-01380-ga9820e12db18-dirty (Apr 25 2025 - 09:40:45 -0300)

CPU:   NXP i.MX8MMQ Rev1.0 A53 at 1200 MHz
CPU:   Consumer temperature grade (0C to 95C) at 42C
Model: FSL i.MX8MM EVK board
DRAM:  2 GiB
Core:  188 devices, 24 uclasses, devicetree: separate
WDT:   Started watchdog at 30280000 with servicing every 1000ms (60s timeout)
MMC:   fsl_esdhc mmc at 30b50000: no vqmmc-supply
****** sdhc clk is 200000000

If I do:

--- a/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi
@@ -614,8 +614,6 @@
 };

 &usdhc2 {
-       assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
-       assigned-clock-rates = <200000000>;
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
        pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;

Then the pause is gone, but the printed clock is incorrect:

U-Boot SPL 2025.04-01380-ga9820e12db18-dirty (Apr 25 2025 - 09:52:28 -0300)
No pmic
WDT:   Started watchdog at 30280000 with servicing every 1000ms (60s timeout)
SEC0:  RNG instantiated
Trying to boot from MMC1
****** sdhc clk is 1431655607

Adam, imx8mm-beacon does not have the
assigned-clocks/assigned-clock-rates properties.

Maybe this is why you haven't observed the problem?