[PATCH] stm32mp: Fix handling of OPTEE in the middle of DRAM

[Patrice CHOTARD]

On 11/19/25 00:17, Marek Vasut wrote:
> STM32MP13xx may have OPTEE-OS at 0xdd000000 even on systems with 1 GiB
> of DRAM at 0xc0000000, which is not the end of DRAM anymore. This puts
> the OPTEE-OS in the middle of DRAM. Currently, the code sets RAM top to
> 0xdd000000 and prevents the DRAM range past OPTEE at 0xe0000000..0xffffffff
> from being set as cacheable and from being usable. The code also sets the
> area over OPTEE as invalid region in MMU tables, which is not correct.
> 
> Adjust the code such, that it only ever sets RAM top just before OPTEE
> in case the OPTEE is really at the end of DRAM, mainly to be backward
> compatible. Furthermore, adjust the MMU table configuration such, that
> the regions over the OPTEE are simply skipped and not reconfigured, and
> the regions between end of OPTEE and RAM top are set as cacheable, if
> any actually exist.
> 
> Signed-off-by: Marek Vasut <marek.vasut at mailbox.org>
> ---
> Cc: Patrice Chotard <patrice.chotard at foss.st.com>
> Cc: Patrick Delaunay <patrick.delaunay at foss.st.com>
> Cc: Tom Rini <trini at konsulko.com>
> Cc: u-boot at lists.denx.de
> Cc: u-boot at dh-electronics.com
> Cc: uboot-stm32 at st-md-mailman.stormreply.com
> ---
>  arch/arm/mach-stm32mp/dram_init.c    |  4 +++-
>  arch/arm/mach-stm32mp/stm32mp1/cpu.c | 11 ++++++-----
>  2 files changed, 9 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
> index 34b958d7afd..e36e42e7c61 100644
> --- a/arch/arm/mach-stm32mp/dram_init.c
> +++ b/arch/arm/mach-stm32mp/dram_init.c
> @@ -65,6 +65,7 @@ int dram_init(void)
>  
>  phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
>  {
> +	phys_addr_t top = gd->ram_top;
>  	phys_size_t size;
>  	phys_addr_t reg;
>  	u32 optee_start, optee_size;
> @@ -86,7 +87,8 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
>  	/* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */
>  	if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) {
>  		if (!optee_get_reserved_memory(&optee_start, &optee_size))
> -			reg = ALIGN(optee_start - size, MMU_SECTION_SIZE);
> +			if (optee_start + optee_size == top)
> +				reg = ALIGN(optee_start - size, MMU_SECTION_SIZE);
>  	}
>  
>  	/* before relocation, mark the U-Boot memory as cacheable by default */
> diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
> index e0c6f8ba937..252aef1852e 100644
> --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
> +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
> @@ -82,11 +82,12 @@ void dram_bank_mmu_setup(int bank)
>  	     i++) {
>  		addr = i << MMU_SECTION_SHIFT;
>  		option = DCACHE_DEFAULT_OPTION;
> -		if (use_lmb &&
> -		    (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) ||
> -		     (gd->ram_top && addr >= gd->ram_top))
> -		   )
> -			option = 0; /* INVALID ENTRY in TLB */
> +		if (use_lmb) {
> +			if (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP))
> +				continue;
> +			if (gd->ram_top && addr >= gd->ram_top)
> +				option = 0; /* INVALID ENTRY in TLB */
> +		}
>  		set_section_dcache(i, option);
>  	}
>  }


Hi Marek

Reviewed-by: Patrice Chotard <patrice.chotard at foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard at foss.st.com>

Tested on stm32mp135f-dk and stm32mp157c-dk2 boards.

Thanks
Patrice