[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

Ralph Siemsen <ralph.siemsen at linaro.org> 於 2025年12月4日週四 下午11:47寫道：
>
> On Wed, Dec 3, 2025 at 3:52 PM Ralph Siemsen <ralph.siemsen at linaro.org> wrote:
> > Then it sounds like it is a recent issue... hmm... I'm currently on
> > 2025.10 release version (plus some cherry-picks). I'll give a try on
> > master/next once I get some other things stabilised...
>
> Just a quick note to say that master branch (with Jan's v2 patches) is
> working fine for me. The calibration is passing on both cold/warm
> reboot, as well as power cycling (I tried a few dozen times each).
> Note that my board only has 512 MB.

Thank you. Yet, no confirmation on 2GB situation. For 1G or 512M
I can also repeat normal boot on different brand.
Which for 512x16 ddr3 die can have several construction from the beginning.
But the question still holds "WHY" CYCLIC or WDT can trigger a normal boot?
Cannot explain nor trace.

Brian

>
> Regards,
> Ralph