[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

Hi Tom,

Tom please reject his patch, thank you.

Hi Alif, and Ralph,

As you both had undergo a board test.
First sorry for cont'd bothering both of you.

If possible I would like to check if this is aligned disregarded to DRAM size.
On U-Boot latest or after 2025.07.

Issue 1:
sequencer.c if turned on debug by including this at the very top.
"#define LOG_DEBUG" and "#define DLEVEL 1 or 2"
If will stall somehow on any brand of board my side current had.

Issue 2:
For DRAM size larger than 1GB, when w/o O.C. and using as stable
setting as possible.
Even it passed the calibration it will not cont'd boot when
sdram_gen5.c is turned on debug flag via "#define LOG_DEBUG"
However this issue is not found on 1GB nor 512MB.

Finding 1:
This is very puzzling and completely lost control on what possible cause.
If SDRAM fails same WDT or CYCLIC simply bypassed it.
Aka 533MHz DRAM speed then it is a must to discover bitflip or any issue
under distro test tools "memtester" or "stressapptest" on long sanity test.
However neither of those return issue since the board used for development.

Finding 2
So long story short WDT or CYCLIC is not a solution to fix SDRAM
calibration fail.

Thanks,
Brian

> > On Wed, Dec 3, 2025 at 3:52 PM Ralph Siemsen <ralph.siemsen at linaro.org> wrote:
> > > Then it sounds like it is a recent issue... hmm... I'm currently on
> > > 2025.10 release version (plus some cherry-picks). I'll give a try on
> > > master/next once I get some other things stabilised...
> >
> > Just a quick note to say that master branch (with Jan's v2 patches) is
> > working fine for me. The calibration is passing on both cold/warm
> > reboot, as well as power cycling (I tried a few dozen times each).
> > Note that my board only has 512 MB.
>
> Thank you. Yet, no confirmation on 2GB situation. For 1G or 512M
> I can also repeat normal boot on different brand.
> Which for 512x16 ddr3 die can have several construction from the beginning.
> But the question still holds "WHY" CYCLIC or WDT can trigger a normal boot?
> Cannot explain nor trace.
>
> Brian
>
> >
> > Regards,
> > Ralph