[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Ralph Siemsen]

Hi Brian,

On Thu, Dec 4, 2025 at 1:09 PM Sune Brian <briansune at gmail.com> wrote:

> If possible I would like to check if this is aligned disregarded to DRAM size.
> On U-Boot latest or after 2025.07.

Sorry for the delay. I am testing on 2025.10 version with a few
additional changes. It is a custom board using its own Quartus memory
parameters (which have been unchanged in many years).

> Issue 1:
> sequencer.c if turned on debug by including this at the very top.
> "#define LOG_DEBUG" and "#define DLEVEL 1 or 2"
> If will stall somehow on any brand of board my side current had.

I also encountered this, but it was solved by disable the watchdog, by
toggling L4WD0 reset. After doing this, there is no problem with using
DLEVEL 2. I even took it a step further and logged every single write
to the DDR control registers.

> Issue 2:
> For DRAM size larger than 1GB, when w/o O.C. and using as stable
> setting as possible.
> Even it passed the calibration it will not cont'd boot when
> sdram_gen5.c is turned on debug flag via "#define LOG_DEBUG"
> However this issue is not found on 1GB nor 512MB.

I was able to get access to board with 2GB, and it boots successfully.
Memory calibration completes, and subsequent test with u-boot "mtest"
basic memory test is also passing.

I'm also running memtester on my 512MB board and it hasn't found any
issues after a few hours runtime.

Regards,
Ralph