[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

Hi Ralph,

On Fri, Dec 12, 2025 at 1:36 AM Ralph Siemsen <ralph.siemsen at linaro.org> wrote:
>
> Hi Brian,
>
> On Thu, Dec 4, 2025 at 1:09 PM Sune Brian <briansune at gmail.com> wrote:
>
> > If possible I would like to check if this is aligned disregarded to DRAM size.
> > On U-Boot latest or after 2025.07.
>
> Sorry for the delay. I am testing on 2025.10 version with a few
> additional changes. It is a custom board using its own Quartus memory
> parameters (which have been unchanged in many years).
>
> > Issue 1:
> > sequencer.c if turned on debug by including this at the very top.
> > "#define LOG_DEBUG" and "#define DLEVEL 1 or 2"
> > If will stall somehow on any brand of board my side current had.
>
> I also encountered this, but it was solved by disable the watchdog, by
> toggling L4WD0 reset. After doing this, there is no problem with using
> DLEVEL 2. I even took it a step further and logged every single write
> to the DDR control registers.

For issue 1 it is just a debug issue but I could also try a bit of your method.
Didn't deeply investigate this.

>
> > Issue 2:
> > For DRAM size larger than 1GB, when w/o O.C. and using as stable
> > setting as possible.
> > Even it passed the calibration it will not cont'd boot when
> > sdram_gen5.c is turned on debug flag via "#define LOG_DEBUG"
> > However this issue is not found on 1GB nor 512MB.
>
> I was able to get access to board with 2GB, and it boots successfully.
> Memory calibration completes, and subsequent test with u-boot "mtest"
> basic memory test is also passing.

For your 2GB case it is w/o CYCLIC and WDT right?
For this may I ask what DDR3 speed you used? 400MHz?
For 2GB there are different die configurations 512x16 itself also come with
different forms. If possible can you provide the actual die part #?

For the latest test result.
1) all boards can run properly w/o watchdog or cyclic but only works on
400M on any size from 512M to 2G.
2) For die itself it is shown that twice die performs much more stably.
3) The DDR calibration itself is so touchy on time and opening CYCLIC or
WDT highly improves the bootup stability on all timing bins.

>
> I'm also running memtester on my 512MB board and it hasn't found any
> issues after a few hours runtime.
>

The most puzzling part is this. It only dies on the U-Boot stage.
The ddr sequence.c was somehow cropped to a point for only size and
speed for the file comments.
All boards or cases that even by luck passed the calibration phase on U-Boot
do not have any issue on all stressapptest nor memtester under distro.

> Regards,
> Ralph